SPI timing Lead/Lag times in iMX8 datasheet

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SPI timing Lead/Lag times in iMX8 datasheet

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YukioOyama
Contributor III

Hi all,

In i.MX 8QuadMax Industrial Applications Processors datasheet,

(Document Number: IMX8QMIEC Rev. 1, 04/2022)

In the table60, "SPIx_CSy Lead Time" and "SPIx_CSy Lag Time".
FCLK_PERIOD are divided by the PRESCALE value, but I think it is correct that FCLK_PERIOD should be multiplied by the PRESCALE value.
If the FCLK_PERIOD is divided by the PRESCALE value, the FCLK_PERIOD will be shorter. The FCLK frequency will be very high.

Am I wrong? Or has an errata been issued?

YukioOyama_0-1661329871489.png

Best Regards,

Yukio Oyama

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AldoG
NXP TechSupport
NXP TechSupport

Hello @YukioOyama-san,

I have confirmation from team that this is a typo, it is now reported to documentation team, thank you for spoting it.

Best regards,
Aldo.

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AldoG
NXP TechSupport
NXP TechSupport

Hello,

I think that it may be confusing, since the Lead and Lag time needs to be tiny, it is in ns. So it is correct to be divided by the PRESCALE.

At the same time FCLK frequency is in MHz

Best regards,
Aldo.

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YukioOyama
Contributor III

Hello Aldo-san,

Thanks for the support.
Could you please tell me with a concrete example.

When FCLK=120MHz, FCLK_PERIOD is 8.3[ns].
Assuming PRESCALE=3, FCLK_PERIOD/2^PRESCALE=1.04[ns].

Assuming PCSSCK=0, the Lead time is
FCLK_PERIOD(PCSSCK+1)/2^PRESCALE-3[ns].
= -1.96[ns].
This is a negative value, is it correct?

I may have misunderstood some parameters. Are there any unusual values I have assumed?

Best Regards,

Yukio Oyama

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AldoG
NXP TechSupport
NXP TechSupport

Hi,

Well it is incorrect, please note that it is + not -, so in your same example:

When FCLK=120MHz, FCLK_PERIOD is 8.3[ns].

Assuming PRESCALE=3, FCLK_PERIOD/2^PRESCALE=1.04[ns].

Assuming PCSSCK=0, the Lead time is

FCLK_PERIOD(PCSSCK+1)/2^PRESCALE+3[ns].

= 4.04[ns].

Best regards,
Aldo.

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YukioOyama
Contributor III

Hi Aldo-san,

In my first question, I made a mistake in the document to which I should have referred. The correct reference was Table 59 and the Lead time.

 

YukioOyama_0-1661732669441.png

It is "+3" at 40 MHz (1.8 V I/O) but "-3" at 60 MHz I/F.
And when calculated, it is negative.

I did not check enough when I posted my question. My apologies for confusing you.

 

Best Regards,

Yukio Oyama

 

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AldoG
NXP TechSupport
NXP TechSupport

Hello Yukio Oyama-San,

I think this may be a typo in the datasheet I'll check with team if this is the case and update as soon as possible.

Best regards,
Aldo.

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AldoG
NXP TechSupport
NXP TechSupport

Hello @YukioOyama-san,

I have confirmation from team that this is a typo, it is now reported to documentation team, thank you for spoting it.

Best regards,
Aldo.

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YukioOyama
Contributor III

Hello Aldo-san,

I understand that is a typo.
I thank you for your faithful support.

Best Regards,

Yukio Oyama

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