SPI receive error with mxs-spi

[lategoodbye]

Hello Freescale Community,

i'm stuck to make the i.MX28 (SPI master) communicate with an IC (SPI slave) over MXS-SPI (using Mainline Kernel 3.10, imx-bootlets 10.12.01) on a custom board (similar to i.MX28 EVK).

mxs-spi 80014000.ssp: registered master spi1

spi spi1.0: setup mode 3, 8 bits/w, 1000000 Hz max --> 0

mxs-spi 80014000.ssp: registered child spi1.0

The SPI work, but in the response are always 2 bits wrong. The i.MX28 sends an 16bit SPI read command ( 0xDA 0x00) in so called burst mode (no chip select toggling between read and write command) to the IC. The response in the i.MX28 should be always 0xAA 0x55, but it's always 0xAB 0x54.

AA 55 = 1010 1011 0101 0100

AB 54 = 1010 1010 0101 0101

If i connect a logic analyser to capture the traffic, i see the correct response 0xAA 0x55. So the problem must be on the i.MX28.

SPI parameter

clock frequency: 1 MHz

Mode: 3

CS: active low

Also i add a printk in the function mxs_spi_txrx_pio() to see what is received low level, but it's always the wrong value 0xAB 0x54.

Does anybody have a idea what's the problem?

Edit:

Here is the important part of the dts file:

ssp2: ssp@80014000 {

                #address-cells = <1>;

                #size-cells = <0>;

                compatible = "fsl,imx28-spi";

                pinctrl-names = "default";

                pinctrl-0 = <&spi2_pins_a>;

                status = "okay";

                spidev@0x00 {

                            compatible = "spidev";

                            spi-cpha;

                            spi-cpol;

                            spi-max-frequency = <1000000>;

                            reg = <0>;

                    };

};

[lategoodbye]

I think i've found the cause for the problem:

https://community.freescale.com/thread/290209

[lategoodbye]

As an answer to the question of Jorge, i have dumped the clock control register (if the problem is reproducable):

clk-imx28: HW_CLKCTRL_FRAC0 = 0x9E9E5513

clk-imx28: HW_CLKCTRL_CLKSEQ = 0x00004104

clk-imx28: HW_CLKCTRL_SSP2 = 0x80000001

The idea of Grzegorz Kotarba with bypassing the clock signal ref_io1 and use ref_xtal instead works like a charm (set BYPASS_SSP2 in HW_CLKCTRL_CLKSEQ):

cat /sys/kernel/debug/clk/clk_summary

   clock                        enable_cnt  prepare_cnt  rate

---------------------------------------------------------------------

ref_xtal                       5           5            24000000

[...]

    ssp2_sel                    1           1            24000000

       ssp2_div                 1           1            24000000

          ssp2                  1           1            24000000

[...]

Does anybody know how to enable bypass in device tree file instead of patching clk-imx28.c?