SPI Garbage Data Issue while Integrating i.MX 8QXP with S32K146

[subash_p]

Hi NXP Support Team,

We are working on integrating an i.MX 8QXP custom board with an S32K146 MCU over SPI. The setup involves sending data from the S32K146 to the i.MX 8QXP, but we are encountering an issue where the i.MX 8QXP receives garbage values instead of the expected data.

Configuration Details:

S32K146 SPI Clock Frequency: 8 MHz

i.MX 8QXP Device Tree Configuration:

&lpspi0 {
fsl,spi-num-chipselects = <1>;
pinctrl-names = "default";
assigned-clock-rates = <60000000>;
pinctrl-0 = <&pinctrl_lpspi0 &pinctrl_lpspi0_cs>;
cs-gpios = <&lsio_gpio1 8 GPIO_ACTIVE_LOW>;
status = "okay";

spidev0: spi@0 {
reg = <0>;
compatible = "rohm,dh2228fv";
spi-max-frequency = <8000000>;
};
};

Updated the i.MX 8QXP device tree to include the LPSPI0 configuration with spidev and ensured the spi-max-frequency was set to 8 MHz.

[Chavira]

HI @subash_p!
Thank you for contacting NXP Support!

Can you try  to add the property spi-slave; to the node lpspi0?

&lpspi0 {
fsl,spi-num-chipselects = <1>;
pinctrl-names = "default";
assigned-clock-rates = <60000000>;
pinctrl-0 = <&pinctrl_lpspi0 &pinctrl_lpspi0_cs>;
cs-gpios = <&lsio_gpio1 8 GPIO_ACTIVE_LOW>;

spi-slave;
status = "okay";

spidev0: spi@0 {
reg = <0>;
compatible = "rohm,dh2228fv";
spi-max-frequency = <8000000>;
};
};

Best Regards!

Chavira

[subash_p]

Here's the corrected version of your paragraph for posting on the forum:

---

Hi @Chavira,

Thank you for your response.

After adding the changes to the DTS file, the spidev device is not created in the /dev/ partition, and I encountered the following error:

[ 2.654396] spi_slave spi1: /bus@5a000000/spi@5a000000/spi@0 is not called 'slave'
[ 2.662047] spi_slave spi1: Failed to create SPI device for /bus@5a000000/spi@5a000000/spi@0

Initially, my DTS configuration looked like this:

&lpspi0 {
    fsl,spi-num-chipselects = <1>;
    pinctrl-names = "default";
    assigned-clock-rates = <60000000>;
    pinctrl-0 = <&pinctrl_lpspi0 &pinctrl_lpspi0_cs>;
    cs-gpios = <&lsio_gpio1 8 GPIO_ACTIVE_LOW>;

    spi-slave;
    status = "okay";

    spidev0: spi@0 {
        reg = <0>;
        compatible = "rohm,dh2228fv";
        spi-max-frequency = <8000000>;
    };
};

To resolve this, I made the following changes to the DTS file:

&lpspi0 {
    fsl,spi-num-chipselects = <1>;
    pinctrl-names = "default";
    assigned-clock-rates = <60000000>;
    pinctrl-0 = <&pinctrl_lpspi0 &pinctrl_lpspi0_cs>;
    cs-gpios = <&lsio_gpio1 8 GPIO_ACTIVE_LOW>;
    status = "okay";

    spidev0: spi@0 {
        reg = <0>;
        spi-slave;
        compatible = "rohm,dh2228fv";
        spi-max-frequency = <8000000>;
    };
};

After applying these changes, the error was resolved, and spidev1.0 was successfully created in the /dev/ partition.

I then wrote the SPI slave receive code for the i.MX8QXP side. Upon running the code, I checked the clock waveform with a logic analyzer. The clock signal is in the active high and low format, but for SPI slave mode, it needs to be in an active low state.

Could you please help me with how to configure the clock polarity to ensure it's in active low for SPI slave mode?

Best Regards!

Subash

[Chavira]

Hi @subash_p!

The clock is given by the master in this case is the S32K Microcontroller, but i am not sure if the property cs-gpios is the root cause of this behavior.

To use the SPI as a slave device the property cs-gpios should be deleted.

The final device tree should be the next:

&lpspi0 {
    fsl,spi-num-chipselects = <1>;
    pinctrl-names = "default";
    assigned-clock-rates = <60000000>;
    pinctrl-0 = <&pinctrl_lpspi0 &pinctrl_lpspi0_cs>;
    status = "okay";

    spidev0: spi@0 {
        reg = <0>;
        spi-slave;
        compatible = "rohm,dh2228fv";
        spi-max-frequency = <8000000>;
    };
};

You can take as a reference the next community post is for iMX93 but the device tree configurations should be similar to your case.

Best Regards!

Chavira

[subash_p]

Hi @Chavira,

After adding the provided patch to my DTS file, the clock pin remains low, but the chip select pin toggles between high and low. I also tried the solution mentioned in this NXP community post, but the SPI slave exhibits the same behavior.

Best Regards!

Subash