SDRAM CLK Assignment

[mrudangshelat]

Hi, I was referring SABRESDB (SPF-27516_C5) for my ongoing design. Is there any specific reason to assign SDCLK1 to Lower DATABUS DRAM_D[31:0] and SDCLK0 to Higher DATABUS DRAM_D[63:32]? I would like to know because generally I have seen SDCLK1 to higher DATABUS DRAM_D[63:32 and SDCLK0 to lower DATABUS DRAM_D[31:0]. Regards, Mrudang

[igorpadykov · Accepted solution]

Hi Mrudang

there is no special reason as both signals are identical.

Best regards

igor

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[mrudangshelat]

Hi Igor,

If I use CLK1 instead of CLK 0 for lower data-bus D[15:0], A[15:0] and other controller will be having interfaced on CS0, CKE0 and ODT0.

1. Does it effect power consumption of DDR SDRAM?
2. Do iMX6 has Single or Dual DDR Controller/channel?

Regards,

Mrudang