SAI1 mclk output waveform IMX6G2 microchip

[59174711]

Hi all,

I'm developing beep audio feature with imx6g2 micro and used the SAI1 MCLK interface to output a reference clock for an audio converter (that is TI tlv320dac3100). My SAI1 mclk output is a waveform similar to a sine wave. Is it correct?

Here's my code to configure sai1 clock root.

const clock_audio_pll_config_t g_ccmConfigAudioPll =
{
.loopDivider = 30,
.postDivider = 2,
.numerator = 72,
.denominator = 100
};

/* Set SAI1 MCLK pin mux */
IOMUXC_SetPinMux(IOMUXC_CSI_DATA01_SAI1_MCLK, 6U);
IOMUXC_SetPinConfig(IOMUXC_CSI_DATA01_SAI1_MCLK,
IOMUXC_SW_PAD_CTL_PAD_DSE(7U) |
IOMUXC_SW_PAD_CTL_PAD_SPEED(2U));

/* Enable SAI1 MCLK output */
IOMUXC_GPR_GPR1 |= IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK;
/* Enable PLL4 608.64M */
CLOCK_InitAudioPll(&g_ccmConfigAudioPll);
/* Set SAI source to PLL4*/
CLOCK_SetMux(kCLOCK_Sai1Mux, 2);
/* Set SAI pre-divider to 6 */
CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 5U);
/* Set SAI divider to 10 */
CLOCK_SetDiv(kCLOCK_Sai1Div, 9U);

And the following pic is my sai1.mclk waveform captured from the scope. Output frequency is 6.16MHz.

[igorpadykov]

Hi Damon

sine waveform may be caused by weak drive strength and capacitive load,

one can try to increase drive strength using DSE field in

SW_PAD_CTL_PAD_x_y SW PAD Control Register described in IOMUX Chapter

of Reference Manual

Best regards
igor
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[59174711]

I tried your suggestion, but it didn't work. Before I set the DSE value to 7, I tried value 2 as you told me. The result is no change.

[igorpadykov]

one can also try to decrease mclk frequency.

Best regards
igor