Hi，
从I.MX6UL的clock tree来看，SAI的时钟源来自PLL4，系统配置PLL4输出为786432000Hz，经过多次分频之后，得到BCLK。因此，BCLK的实际输出频率与786432000Hz相除，必须是整数。而您需要的2个时钟，都不是整数倍，因此得不到这2个时钟。
&clks {
assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
assigned-clock-rates = <786432000>;
另外，BCLK时钟的输出，是CPU工作在Master模式时，声卡驱动和平台端SAI驱动根据实际播放的音频文件进行配置的，如果不能整除，也会输出一个与理论BLCK非常接近的时钟，让音频播放出来。
如果您正在调试audio codec，您可以配置CPU端I2S为Slave模式，codec做Master模式，由codec提供 BCLK和LRCLK时钟及左右声道同步信号给CPU端。那么，你可以利用codec的PLL配置输出你所需要的频率。
-------------In English--------------
According to the clock tree of i.mx6ul, the clock source of Sai comes from pll4. The system configures the output of pll4 as 786432000hz. After multiple frequency division, BCLK is obtained. Therefore, the actual output frequency of BCLK is divided by 786432000hz and must be an integer. The two clocks you need are not integral multiples, so you can't get them.
In addition, when the CPU is working in master mode, the output of the BCLK clock is configured by the sound card driver and the Sai driver at the platform end according to the actual played audio file. If it can't be divided, it will also output a clock very close to the theoretical blck to play the audio.
If you are debugging audio codec, you can configure I2S on CPU side as slave mode and codec as master mode. Codec provides BCLK and lrclk clocks and left and right channel synchronization signals to CPU side. Then, you can use codec's PLL configuration to output the frequency you need.
-------------------------------------------
Have a nice day!
BR,
Wedong
