RT1050 SDRAM Pin Configuration Question

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RT1050 SDRAM Pin Configuration Question

Contributor III


I am using a custom board based off the MIMXRT1050-EVKB board. I was having issues with my external SDRAM in which running a memory test would fail. The memory test consists of writing a value to an address in SDRAM then reading it back to confirm that value.

I am using the SEMC example as a template for my own software project. Something I noticed was that in the pin mux configuration of the SEMC SDRAM pins, all the pins besides the DQS pin were set to be used as SEMC pins. In the Pin configuration, the SEMD_DQS pin is set as FLEXPWM1_PWM3_B by default from the given NXP example.

I believe this is done because on the RT1050 board, the DQS pin is not used. Therefore, if it is set as a SEMC DQS pin then the SEMC will be looking at the pin for information when it is not tied to anything, which will cause errors with the SDRAM.

My question is, why were all the pins on the SEMC SDRAM configuration set up to be used as SEMC pins besides the DQS pin?


Kamal Nasif

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NXP Employee
NXP Employee

Hello Kamal,

Hope you are doing well.

In the SDK example for semc_sdram. You will find that the default configuration for the dqs signal is to be looped back internally. Essentially the semc_dqs signal is a dummy read strobe loop back pad. You may find the details of this in section 25.3 of the reference manual. 

The SDRAM we have on the EVK is an SDR SDRAM which does not make use of this signal. Please review the datasheet of your SDRAM to see if this signal is required in your design.

Best Regards,



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