Sorry to Write direct question.
From RT1020 referencs manual , Chapter 16 PMU
Question 1.
what is it xPU from PMU_MISC2 -> REG2_BO_OFFSET & REG1_BO_OFFSET ?
what it is Core power domain from PMU_MISC2 -> REG0_BO_OFFSET ?
Is it component (hadware part) of EVK Board ?
Question 2.
Brown-out event generate interrupt IRQ_DIG_BO, Can it be handled by PMU_IRQHandler ?
Do I need to re-define this function? How Can I clear this interrupt flag? flag value is PMU_MISC1->IRQ_DIG_BO , Is it right?
Or Hardware Reset ?, not controlled by software ?
Qusetion 3.
I couldn`t find the setting code from all SDK example. that means , this value is set from manufacturing process?
Because When I dump the address,, the result is [ 0x400D8110: 0x 00021073 ]
this mean, 0x400D8110 is PMU_REG_1P1 , and last 4bit, “3” meaning include “Enable BO”
I thought, this “someone set this address.”
Is there any example about Brown out value ?
Qusetion 4.
From Table 4-2. CM7 domain interrupt summary
this mean that [2 ea xPU power Domain & Core Power Domain of Brown-out ] does not generate PMU interrupt ??? ,, only 1.1 2.5 3.0 regulator brown out ?
Qusetion 5. Is Brown-out reset not recorded on SRC->SRSR ??
Is it category of [Power on Reset .. source] ? then How can I recognize Brown-out from SRC->SRSR ?
Hello @Seongyon_Jeong,
We are terribly sorry for the delay to answer you.
Brown-out event generate interrupt IRQ_DIG_BO, Can it be handled by PMU_IRQHandler ?
In the i.MX RT1020 Processor Reference Manual. Section 16.1. Chip-specific PMU information it is mentioned that IRQ_DIG_BO is reserved and not applicable to this device. You might want to check the LDO specific flags, for example, the BO_VDD1P1. They could be handled by a PMU interruption handler.
Do I need to re-define this function?
What do you mean for re-define? Could you please take a look at the following community post? It could be useful: How to enable brownout detection - NXP Community.
How Can I clear this interrupt flag? flag value is PMU_MISC1->IRQ_DIG_BO , Is it right? Or Hardware Reset ?, not controlled by software ?
The flag only would be cleared if you fix the voltage to the value needed.
I couldn`t find the setting code from all SDK example. that means , this value is set from manufacturing process?
As you mentioned, if the customer does not modify the registers, the registers will have a default setting.
Is there any example about Brown out value ?
Unfortunately, there are not examples of how to work with brown-out detection. Nonetheless, you could check the implementation done here: How to enable brownout detection - NXP Community. It could be helpful.
From Table 4-2. CM7 domain interrupt summary
this mean that [2 ea xPU power Domain & Core Power Domain of Brown-out ] does not generate PMU interrupt ??? ,, only 1.1 2.5 3.0 regulator brown out ?
The interruptions that would be detected, as you mentioned, are either the 1.1, 2.5 or 3.0 LDO regulators. The xPU and Core Power Domain does not have brownout detection as you might see in the PMU_REG_COREn register and Section 16.1.1. Chip-specific PMU information., where it is mentioned that some bitfields are not applicable on this device, and those corresponding bits are Reserved.
Is Brown-out reset not recorded on SRC->SRSR ??
Is it category of [Power on Reset .. source] ? then How can I recognize Brown-out from SRC->SRSR ?
In the i.MX RT1020 Processor Reference Manual. Section 21.6.2. Internal POR., mentions that if the external SRC_POR_B signal is not used (always held high or left unconnected), the processor defaults to the internal POR function (PMU controls generation of the POR based on the power supplies).
You could see in Figure 21-5. SCR inputs and outputs that the POR -> SCR_POR_B is named ipp_reset_b which is the SCR->SRSR bit you could use to recognize a brown-out reset.
Kind regards, Raul.
Hello @Seongyon_Jeong,
We are terribly sorry for the delay to answer you.
Brown-out event generate interrupt IRQ_DIG_BO, Can it be handled by PMU_IRQHandler ?
In the i.MX RT1020 Processor Reference Manual. Section 16.1. Chip-specific PMU information it is mentioned that IRQ_DIG_BO is reserved and not applicable to this device. You might want to check the LDO specific flags, for example, the BO_VDD1P1. They could be handled by a PMU interruption handler.
Do I need to re-define this function?
What do you mean for re-define? Could you please take a look at the following community post? It could be useful: How to enable brownout detection - NXP Community.
How Can I clear this interrupt flag? flag value is PMU_MISC1->IRQ_DIG_BO , Is it right? Or Hardware Reset ?, not controlled by software ?
The flag only would be cleared if you fix the voltage to the value needed.
I couldn`t find the setting code from all SDK example. that means , this value is set from manufacturing process?
As you mentioned, if the customer does not modify the registers, the registers will have a default setting.
Is there any example about Brown out value ?
Unfortunately, there are not examples of how to work with brown-out detection. Nonetheless, you could check the implementation done here: How to enable brownout detection - NXP Community. It could be helpful.
From Table 4-2. CM7 domain interrupt summary
this mean that [2 ea xPU power Domain & Core Power Domain of Brown-out ] does not generate PMU interrupt ??? ,, only 1.1 2.5 3.0 regulator brown out ?
The interruptions that would be detected, as you mentioned, are either the 1.1, 2.5 or 3.0 LDO regulators. The xPU and Core Power Domain does not have brownout detection as you might see in the PMU_REG_COREn register and Section 16.1.1. Chip-specific PMU information., where it is mentioned that some bitfields are not applicable on this device, and those corresponding bits are Reserved.
Is Brown-out reset not recorded on SRC->SRSR ??
Is it category of [Power on Reset .. source] ? then How can I recognize Brown-out from SRC->SRSR ?
In the i.MX RT1020 Processor Reference Manual. Section 21.6.2. Internal POR., mentions that if the external SRC_POR_B signal is not used (always held high or left unconnected), the processor defaults to the internal POR function (PMU controls generation of the POR based on the power supplies).
You could see in Figure 21-5. SCR inputs and outputs that the POR -> SCR_POR_B is named ipp_reset_b which is the SCR->SRSR bit you could use to recognize a brown-out reset.
Kind regards, Raul.
