RAW10 (SBGGR10) support in imx8qxp

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RAW10 (SBGGR10) support in imx8qxp

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Contributor I

Hi,

I am facing problem in getting proper data from camera (RAW10bit, 2lanes) using MIPI-CSI-0. In each pixel(16bits), 4-MSB bits are getting discarded.

Input & output formats of ISI is set to RAW10

Anyone else is facing the same issue with RAW10 format in imx8qxp? Any lead is appreciated.

Thanks

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5 Replies

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NXP TechSupport
NXP TechSupport

Statement 1 is right.

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  • If I receive a RAW10 stream, how data will be packed in memory after the ISI (shift + number of byte to be used to have the full data)?

     MIPI subsystem RAW10 output format is  {valid_data, 4’b0} . After right shift 4 bits, you will get the correct image.

-----

There is a mistake in the RM, I´ll ask to fixed. Thanks for the catch.

Regards

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162 Views
Contributor I

I think there is some confusion in the TRM(REV-E): i.MX 8DualX/8DualXPlus/8QuadXPlus Applications Processor Reference Manual

Statement 1:

The CSI data is right LSB aligned and zero padded depending
on data format. When interfacing ISI, CSI data is shifted 6-bits
due to ISI bits [5:0] always being zero
(0bxxCSIDATAxxxxxx). All RAW14, RAW12, RAW10,
RAW8, and RAW6 video data is filled from BIT[13] to LSB,
the remaining bits are zero padded. Only RAW16 input data
will be saved to memory from BIT[15] to LSB.

Statement 2:

001100b - RAW10 - 10-bit RAW data packed into 16-bit WORD with 6 LSBs waste bits

Found that statement 1 doesn't matches with statement 2.

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NXP TechSupport
NXP TechSupport

Hello wasim,

Supported cameras and formats are described in AN12187 Quick Start Guide

for MINISASTOCSI for i.MX 8M Evaluation Kit

https://www.nxp.com/docs/en/application-note/AN12187.pdf 

It support raw10, t1he clocks are MIPI CSI host clocks, they are not related to external camera input signal.

The host can support 1, 2,3 and 4 lanes camera, so 1 lane camera can be supported. The lane number is set from device tree, "data-lanes = <1 2>;" means 2 lanes are used:

 

&mipi_csi_1 {
 #address-cells = <1>;
 #size-cells = <0>;
 status = "okay";
 port {
  mipi1_sensor_ep: endpoint1 {
   remote-endpoint = <&ov5640_mipi1_ep>;
   data-lanes = <1 2>;
  };

  csi1_mipi_ep: endpoint2 {
   remote-endpoint = <&csi1_ep>;
  };
 };
};

 

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Contributor I

Hi BioTICFSL,

Thanks for your reply.

Our SOC is 8QXP MEK and not 8M.

I have tried for both single lane and multi-lane. Our endpoint supports 2 lanes.

Any idea on the documentation of CSI2 Subsystem CSR registers.

Thanks

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162 Views
Contributor I

We tried using single data-lane but still the same issue.

Can anyone help?

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