Questions about the IPU capabilities of imx6q

[LeviathanSteven]

Hi,

Recently I was working on imx6q.

From IMX6DQRM_revC.pdf, we know that imx6q has two IPUs, and each IPU has two DIs. So it seems that it can support 4 independent outputs simultaneously. I gave my understanding in the figure below.

                                                                                                                   If the definition of this figure is not high enough for reading, please get the original picture from the attachment.

My questions is, Can we connected four transmitters(LVDS or HDMI) to all the four DIs, and  then connected four display monitors.  Can they worked   independently and  simultaneously.If yes, what's the HW limitation? Such as can we set each of the display monitors to 1920x1080p@60？？？

Actually this application is a TV Wall, which need four channels input   simultaneously.

Or any other suggestions?

Thanks so much in advance!                                                                                        

[Yuri]

Basically it is possible to connect up to four displays (two displays per IPU) to i.MX6Q.
But performance restriction is as following : combined rate for the two ports is up to 240 MP/sec.  

As for 1920x1080p@60 mode - it requires ~120 MP/sec/. Looks like enough, but note  these rates

refer only to screen refresh, gated by the capabilities of the display port. A full use case typically

includes additional activities.

[LeviathanSteven]

Hi Muhin,

Thanks for your kindly help!

'But performance restriction is as following : combined rate for the two ports is up to 240 MP/sec. ' .

Is that means for each DI, the sum of the connected two monitor's timing's pixel clocks can not be larger than 240M ?

For example, we can connected four monitors with mode 1280x1024@60 to the SOC, because the pixel clock of 1280x1024@60 is 108M, and two of them are 216M, which is smaller than 240M. In this case, the four monitors can work well simultaneously, which is as shown on the figure in my last mail.

Am I right???

Sorry for bothering you,  but I just want to double confirm. Thanks.

[Yuri · Accepted solution]

Please look at my comments below.

1.

> Is that means for each DI, the sum of the connected two monitor's timing's pixel clocks can not be larger than 240M ?

Basically - yes. Let me remind MP/sec relates to Pixels / sec, so it is the same as display frequency, when
single clock is needed per pixel.  

2.

> For example, we can connected four monitors with mode 1280x1024@60 to the SOC, because the pixel clock

> of 1280x1024@60 is 108M, and two of them are 216M, which is smaller than 240M. In this case, the four monitors

> can work well simultaneously, which is as shown on the figure in my last mail.

> Am I right???

Yes, but again, please do not forgot, that these rates refer only to screen refresh, gated by the capabilities of the

display port. A full use case typically includes additional activities.

[LeviathanSteven]

Hi Muhin,

OK, I got it!

Thanks so much for your great help!

[LeviathanSteven]

Any one can help? Can we connect four monitors to the two IPUs???