Question, i.MX6SoloLite power-up sequence

[Aemj]

Dear team,

I would like to ask about the power-up sequence of i.MX6SoloLite.

Are there any restriction on the power-up order of VDD_ARM_IN, SOC_IN, PU_IN and VDD_HIGH_IN?

Can I understand that there is no matter whatever the power-up order of VDD_ARM_IN, SOC_IN, PU_IN and VDD_HIGH_IN is?

Thanks,

Miyamoto

[igorpadykov]

Hi Miyamoto

according to datasheet Power-Up Sequence requirements (below)

there are only some restrictions for VDD_ARM_IN, SOC_IN

Best regards

igor

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