Question, i.MX6Solo SDMA interrupt

[SLICE]

Dear team,

I would like to ask about SDMA of i.MX6Solo.

My customer saw that the interruption of transfer completion could not occur sometimes on their board.

And they have the question as below. Please give your answers to that.

(1) When the bus-access of external DDR or peripherals is conflict with the SDMA transfer, which bus-access has a priority?

(2) When the confliction occur as above, is it possible to change priority by configure SDMAARM_SDMA_CHNPRIn register?

(3) Could you show me whether it is possible not to occur the transfer completion interrupt by any conditions (register setting or something)?

Thanks,

Miyamoto

[art]

1) The DDR controller always has the highest priority. The concurrent access is postponed (but not cancelled).

2) No. The SDMAARM_SDMA_CHNPRIn registers only define the relative priorities of the channels within the SDMA engine, not relative to other bus masters.

3) There seems to be the software issue, such as the interrupt handling code missing the interrupts sometimes for some reason. Please check.

Have a great day,
Artur

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[SLICE]

Hello art‌

Thanks for your answer.

The customer checked your answers, and they have comments as below.

Please give your answers to the below questions.

(1) They are talking about the case of conflict of ‘accessing to external DDR from ARM core’ and ‘accessing to external DDR from SDMA’.

Could you show me which of above access has the higher priority?

They do not mean the priority of DDR controller.

(2) In the above case, if some priority exists, can configuring SDMAARM_SDMA_CHNPRIn register affect to the priority?

(e.g. Setting 7 into SDMAARM_SDMA_CHNPRIn register may cause getting higher priority to ‘accessing DDR from SDMA’? Etc.)

Thanks,

Miyamoto