Question, i.MX6SDL DDR_INPUT setting for DDR3

[Aemj]

Dear team,

I would like to ask about DDR_INPUT mode setting for MMDC signals.

Could you show me which of ‘CMOS input mode’ and ‘Differential’ should be set into DDR_INPUT in the case of using DDR3?

My customer believed that single-ended signals of DDR should be set to CMOS input mode, but it seems to be set to Differential in U-Boot code.

Should the DDR_INPUT of those single-ended signals, such as DRAM_DATAxx, be set to ‘Differential input mode’?

Thanks,

Miyamoto

[Yuri]

  The input mode parameter (DDR_INPUT bit) may be configured as CMOS  or differential.

This configures the voltage level at which the pins senses a transition from logic low to logic high and

vice versa. In differential mode, the pins level transitions are at 50%. In CMOS input mode, the pins level

transitions are  at 80% for high and 20 % for low.  So, strictly speaking, this option should be set as CMOS
for single-ended signals and as Differential for differential ones. But really different DDR_INPUT options may
be used in case of timing problems in order to improve situation.

Have a great day,
Yuri

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