Question, i.MX6Q LDB pix clock setting

[SLICE]

Dear team,

I would like to ask about LDB pix clock setting

My customer needs to know how to set LDB(ldb_di0_ipu/ldb_di1_ipu) pix clock(LVDS_CLK) to 74.25MHz in the case of using 24MHz clock input into i.MX6Q.

In the customer’s understanding, LDB clock(LDB_DI0_SERIAL_CLK_ROOT / LDB_DI1_SERIAL_CLK_ROOT) should be 519.75MHz for making 74.25MHz of pix clock. (512.75MHz = 74.25MHz x 7)

So, they cannot get 74.25MHz of pix clock, accurately, with 24MHz clock.

Is it possible to get 74.25MHz of pix clock with 24MHz clock input?

If yes, please show me the way to configure.

Thanks,

Miyamoto

[joanxie]

I upload the patch for how to change the lvds clock, hope helpful for you.

[SLICE]

Hello Joan,

Could you please show me what can be achieved by applying the patch?

The LDVS clock gets to be 74.25MHz by applying it?

Best Regards,

Miyamoto

[joanxie]

if you use the two LVDS channel lines to drive one screen that has an LVDS clock of 74.25Mhz.

try to set the source code  as below, just see the clock frequency:

====

&ldb {

        status = "okay";

        split-mode;

        lvds-channel@0 {

                fsl,data-mapping = "spwg";

                fsl,data-width = <24>;

                primary;

                status = "okay";

                display-timings {

                        native-mode = <&timing0>;

                        timing0: hsd100pxn1 {

                                clock-frequency = <148500000>;

                                hactive = <1920>;

                                vactive = <1080>;

                                hback-porch = <220>;

                                hfront-porch = <40>;

                                vback-porch = <21>;

                                vfront-porch = <7>;

                                hsync-len = <60>;

                                vsync-len = <10>;

                        };

                };

        };

};

====