Question, clock tree for i.MX6SoloLite UART

[Aemj]

Dear team,

I would like to ask about clock tree for UART of i.MX6SoloLite.

My customer wants to use osc_clk as a source clock of UART for their board.

They do not want to use PLL for the source clock because the PLL setting has to be changed frequently to ‘bypass’.

According to i.MX6SL reference manual, the clock tree is as below.

 

They want to configure UART operation with over 1Mbps bitrate.

And they believe that it is possible when they set a divider into 1/16.(24MHz/16=1.5M)

But after they verified actual behavior of the UART, they believe that the 1/6 divider is added as below.

The UART bitrate on their board was lower than the expected value.

Is it true?

Could you show me what they should do to achieve 1MHz bitrate of UART with the source clock of osc_clk?

Thanks,

Miyamoto

[gusarambula]

Hello Miyamoto,

The path mentioned is correct up to the UART module itself. The UART reference clock path is as shown on the following figure (UART reference clock figure from the i.MX6 Series Firmware Guide) and as you see there is a  pre-divider inside the UART module and the ref_clk output is used to generate the baud rate clock according to the formula available in the section Binary Rate Multiplier (BRM) of the UART block.

Would this match your experience of having a lower frequency than expected?

Regards,

[Aemj]

Hi Gusarambula,

Thanks for your reply.

The figure you showed me seems to describe that PLL3 clock module used for UART clock source contains 1/6 pre-divider. And that will match the clock tree description in i.MX6 reference manual.

But the customer is using 24MHz osc_clk instead of PLL3.

I believe the figure you showed me does not mention about the case of using osc_clk.

If osc_clk module has a 1/6 pre-divider similarly to the PLL3 clock module, the description(figure 15-3 ) in i.MX6SL reference manual is incorrect.

How about that?

Please show me whether or not user can achieve 1Mbps bitrate when using osc_clk for the clock source of UART.

Thanks,

Miyamoto

[gusarambula]

Hello Miyamoto,

The 1/6 divider is fixed for the PLL3 clock. I’m investigating whether this is also true for the 24MHz osc_clk, although from your experience this seems to be the case.

I’ll let you know when I get confirmation on this and in case it’s needed we’ll escalate to the documentation team so this gets addressed on the next release of the documentation.

Regards,

[gusarambula]

Hello Miyamoto,

I confirmed with our experts that the right configuration would be as follow:

Please take this into account when setting the dividers for your desired output. This error will be fixed on the next release of the documentation.

Regards,

[Aemj]

Hi Gusarambula,

Thanks for your confirmation.

Are there any ways to disable the 1/6 divider?

In my customer's board, adding external HW parts is needed for achieving the desired UART bitrate.

Thanks,

Miyamoto

[gusarambula]

Hello Miyamoto,

The 1/6 divider is fixed so I’m afraid there is no way to bypass it or change it. My apologies.

Regards,

[Aemj]

Hi Gusarambula,

Could you specify the date of the next release of the reference manual?

The error on the clock-tree in the current reference manual is very important for the customer. And we believe that the miswritten in the clock-tree can be big impaction for all of the software designer as well.

Actually, they must change the design of the customer’s board for this error, and it affected to the power consumption.

Because they shall keep on using i.MX6 for the designing for their next products, they cannot accept that the miswritten is kept as it is in the reference manual.

Thanks,

Miyamoto