Question about gated clock mode

[zhouwei]

Hello

     I am using i.mx6 to capture 16bit 4:2:2 YUV signal in gated clock mode. but it does not work like what the datesheet says.

     it is said"Pixel clock is valid as long as IPU2_CSIx_HSYNC is high. Data is latched at the rising edge of the valid pixel clocks. IPU2_CSIx_HSYNC goes to low at the end of line. Pixel clocks then become invalid and the CSI stops receiving data from the stream.in IMX6DQCEC(section 4.11.10.2.2 Gated Clock Mode). But real situation is that imx6 would capture data when the rising edge of Hsync comes, and imx6 would not stop capturing data even the falling edge comes.There may be something wrong.

     i haven't found someone using imx6 to capture data correctly in gated clock mode in this community but found many peopel facing the same problem.

     If  there is someone using imx6 to capture data correctly in gated clock mode, could you tell me and give me some advice?

Thanks !

zhou

[lwx]

hi all,

I have same problem too!

Do anybody solve it?

[hanseunglee]

Hello zhou wei.

I have a really same problem !.

If you have a solution or advice, please share for me.

[宗標廖]

Hello,zhou wei

I did a test on i.MX6dlsabresdp(which with an ov5642 camera equipped).

After running /unit_test/mxc_v4l2_capture.out with proper parameters,

I read the CSI0 Sensor Configuration Register(IPU_CSI0_SENS_CONF)

and value for this register was 0x8900.

According to this value,configurations for CSI0 is as below:

1)data width is 8-bit

2)data format is YUV422 (YUYV...)

3)Timings protocol is Gated mode.

So, if my understanding of IPU_CSI0_SENS_CONF register is right,

then you can refer to i.MX6dlsabresdp to resolve your problem.

Best Regards,

ZongbiaoLiao

[igorpadykov]

Hi zhou

for gated mode one can look below

How to Support RGB565 Gated Mode Input to i.MX6 CSI

you are correct that capture occurs on HSYNC edge as confirmed below

Re: IPU v3  CSI0, HSYNC and DATA_EN questions in gated clock mode.

Best regards

igor