Hello,
I have a question about CSIx_SENS_PRTCL bit setteng, between Interlace and Progressive.
When, CSI set to input BT656 interlace like a section "2.1.1 BT.656 Interlace Setting" in
document i.MX6 IPU TVIN Application Note.
In this time, if CSIx_SENS_PRTCL bit change from 0x3(BT.656 interlaced mode)
to 0x2(BT.656 progressive mode), it can capture only field 0 line data because only
detect EAV/SAV pattern setting in IPU_CSI_CCIR_CODE_1 register.
And the IPU_CSI_CCIR_CODE_2 register setting is ignored.
Is it correct?
Best regards,
Ishii.
Hello Igor
Thank you very much for your assistance.
I create new thread as following.
Question about bt.656 progressive video capture function.
I am looking forward to hearing from you.
Best regards,
Ishii.
Hi Ishii
yes this understanding is correct, on p.5 document states:
"IPU_CSI_CCIR_CODE_1, it is for frame EAV/SAV setting
IPU_CSI_CCIR_CODE_2, not used for progressive mode "
Best regards
igor
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Hello
Igor,
Thank you for your quick response.
In Progressive mode, I have three additional questions.
In this time, section "2.5.2 CCIR Register Setting for Progressive Signal" in document
iMX6 IPU TVIN Application Notes say that
"in register IPU_CSI_CCIR_CODE_1, only CSI_STRT_FLD0_BLNK_1ST, CSI_STRT_FLD0_ACTV and
CSI_END_FLD0_ACTV are used, the three bits register value for each region (MSB to LSB) is H, V, F
data, and F is always 0."
1) Why only this three bit field are used?
2) Some video decoder output BT656 progressive data with F bit = 1.
In this time, is this decoder not used with iMX6?
3) How detect a start line of the new frame/ blanking and Active Video area?
Only F,V,H bit pattern match with CSI_CCIR_CODE_1 register bit?
or use some other condition like IPU_CSI_SENS_FRM_SIZE and IPU_CSI_ACT_FRM_SIZE value.
Best regards,
Ishii.
Hi Ishii
for new questions please create new thread.
Best regards
igor