Hi Craig
Clock Controller module may not successfully master the system bus
due to incorrect power-up sequence or external 26MHz clock noise /
noise on OSC26VDD, MPLLVDD power supplies. Note, external clock should
not be provided to unpowered processor, it should be applied along with
OSC26VDD power supply. In general one can check low power mode sequence
by oscillosope outputting MPLL clock on CLKO pin with CCSR register or
check CKE signal with Figure 18-37. SDRAM/LPDDR Enter Self Refresh Mode
During System Sleep Mode i.MX27 RM.
Datasheet on p.28 recommends to disable oscillator circuit with CSCR (OSC26M_DIS)
and apply clock to EXTAL26M. http://cache.freescale.com/files/dsp/doc/data_sheet/MCIMX27EC.pdf
External clock may not have the desired spectral purity, only a crystal will provide the necessary signal quality.
Below oscillator specs

Best regards
igor
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