Pin terminations for PCIE

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Pin terminations for PCIE

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pbain
Contributor III

Hi, part of the design of a new project is using a mSATA flash drive (pSLC). The only connection to the PCIE interface is PCIE_SATA0_TX0_N/P and PCIE_SATA0RX0_N/P. Using a i.MX8QM.
I have worked out some of the terminations based on the reference designs provided, and the Hardware Developers Guide document, but am unsure what to do with the remaining pins. Schematic is attached. Are you able to help?

Thanks,
Peter

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Yuri
NXP Employee
NXP Employee

Hello,

 

 

  Note, the i.MX8 is still in preproduction stage (not fully launched yet), therefore full documentation

is not published.

  Generally You may refer to MCIMX8QM-CPU MEK scheme and “Unused Input / Output

Guidance” in i.MX8 QM/i.MX8 QXP Hardware Developer’s Guide regarding unused (if any)

PCIe.

 

Have a great day,

Yuri

 

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