PCIe pins direction

[tarterkit_ru]

Hello, i want connect to i.MX6S PCIe LAN chip RTL8111E.

In RTL8111E PCIe pins is named as: HSI (input) and HSO (output) signal pair.

But i.MX6 datasheet not have information about PCIE_RX it is output or input pair.

[richard_zhu · Accepted solution]

Hi:
PCIE_TX is output, and PCIE_RX is input.

Best Regard

Richard.

[andyj25]

Hi Hongxing Zhu,

I have a question.

If the RTL8111E can be detected on the i.MX PCIe bus,  should I be able to see it on: /sys/bus/pci_express/devices  ?

Currently I see nothing there.  Does that mean there's something wrong with my hardware?

[richard_zhu]

At least, you can see something by lspci command in Linux consol, if your ep device had been detected by pcie rc.

Richard.

[andyj25]

Hi Richard,

lspci returns nothing.

Here is my schematic segment for the RTL8111E.  Can you spot anything wrong with it?  Thanks!!!

http://i.imgur.com/D4dFP3g.jpg

[richard_zhu]

Hi:

Welcome.

HW is out of my knowledge scope, you can make a reference to the pcie schematic of imx6 sabresd board of fsl.

I found there are some differences on the pull-down of the pcie clk signals between your schematic and fsl's reference  schematic.

Hope it is helpful.

BTW, I'm curious about your "detected” at your side, did the pcie link have been setup between pcie rc and ep,

and the pcie rc allocate the pcie memory space and so on to pcie ep?

Richard

[andyj25]

Hi Richard,

I'm loking at SPF-27516_C3.pdf. There's no RTL8111E on that, but there is PCIe.

Are you referring to the 49.9Ω resistors pulling down CLK1_N and CLK1_P on the sabresd reference schematic?

Andrew

[andyj25]

The added resistors didn't help.  Thanks for your tips though.  We will continue debugging it.

[richard_zhu]

Yes, it is.

[andyj25]

Thanks Richard,

I will patch those resistors and report back here if it works.

In that schematic segment I posted there is also LAN_CLKREQ.   I have muxed it as a GPIO, but it is not implemented anywhere in my board-mx6q_sabresd.c.

Is this pin critical for the operation of the PCIe bus?

Here's a segment from the datasheet: http://i.imgur.com/lAfSahM.png

[richard_zhu]

I think it is not critical for pcie if it is not used at all.