Hello,
We would like to know the mechanisms present in the i.MX8QM to generate PCIe accesses to configuration space, this to be able to write our own PCIe/PCI enumeration software from scratch?
The i.MX8QM reference manual has a PCIe chapter in which the drawing are almost completely unreadable, and the remaining text is also not making us much wiser regarding this aspect.
It seems also that Linux is using some kind of PCIe BIOS to accomplish this, but since we don't use Linux or want to use a BIOS, we need some extra information.
What we need, is to know how we can generate a PCIe configuration cycle to bus #, device #, function #, register_offset #. Typically there are multiple mechanisms foreseen on PCIe root complexes for doing that, based on my past experience:
- Indirect mechanism through the use of two registers; being an address register and a data register.
- Memory mapped mechanism by mapping the buses/devices/functions/register_offsets as a continuous huge memory area of 256 MiB, that when accessed, generates PCIe configuration accesses.
For both mechanisms, we're missing the information inside the i.MX8QM reference manual for doing that?
Is anybody knowing how to do this?
Many thanks!
Kind regards,
ToarteFretter.
