I would like to change the PCIe register settings, but the register address in the "i.MX 7Dual Applications Processor Reference Manual (Rev. 1, 01/2018) " seems to be incorrect.
I think the memory map below is wrong.
PCIE_PHY_CMN memmory map (p.3735)
PCIE_PHY_TRSV memory map (p.3753)
For example, PCIE_PHY_CMN_REG04 is listed as 306D_0016h, but I believe 306D_0010h is correct.
Is it possible to have tell me the correct memory map?
There is a PCIe connected WiFi module that does not link up, and I am planning to investigate whether changing the settings will improve it.
Sincerely,
mio
Solved! Go to Solution.
Dear @mio ,
>>PCIE_PHY_CMN_REG04 is listed as 306D_0016h, but I believe 306D_0010h is correct.
Yes, correct.
The offset address of the PCIE-PHY-CMN-REGxx register should be incremented in hexadecimal accumulation.
Like this:
PCIE_PHY_CMN_REG01 306D_0000h base + 4h offset = 306D_0004h
PCIE_PHY_CMN_REG02 306D_0000h base + 8h offset = 306D_0008h
PCIE_PHY_CMN_REG03 306D_0000h base + 12h offset = 306D_0012h ---> should be : 08+4=0x0C ---- > = 306D_000Ch
PCIE_PHY_CMN_REG04 306D_0000h base + 16h offset = 306D_0016h --- > should be : 0x0C+4=0x10 ---- > = 306D_0010h
PCIE_PHY_CMN_REG05 306D_0000h base + 20h offset = 306D_0020h --- > should be : 0x10+4=0x14 ---- > = 306D_0014h
PCIE_PHY_CMN_REG06 306D_0000h base + 24h offset = 306D_0024h --- > should be : 0x14+4=0x18 ---- > = 306D_0018h
PCIE_PHY_CMN_REG07 306D_0000h base + 28h offset = 306D_0028h --- > should be : 0x18+4=0x1C ---- > = 306D_001Ch
.....
please pay attention to these registers, their suffix digits are hexadecimal.PCIE_PHY_CMN_REG1x should be PCIE_PHY_CMN_REG(1x16+x), for example:
PCIE_PHY_CMN_REG15 is PCIE_PHY_CMN_REG21, it's address should be : 306D_0000h base + 0x54 offset = 306D_0054h (0x54 is the hexadecimal of 21x4=84D)
[Additionally]
Confirmed with internal team, In pcie driver, registers' address are all correct, don't worry!
Thanks!
Regards,
weidong
Dear @mio ,
>>PCIE_PHY_CMN_REG04 is listed as 306D_0016h, but I believe 306D_0010h is correct.
Yes, correct.
The offset address of the PCIE-PHY-CMN-REGxx register should be incremented in hexadecimal accumulation.
Like this:
PCIE_PHY_CMN_REG01 306D_0000h base + 4h offset = 306D_0004h
PCIE_PHY_CMN_REG02 306D_0000h base + 8h offset = 306D_0008h
PCIE_PHY_CMN_REG03 306D_0000h base + 12h offset = 306D_0012h ---> should be : 08+4=0x0C ---- > = 306D_000Ch
PCIE_PHY_CMN_REG04 306D_0000h base + 16h offset = 306D_0016h --- > should be : 0x0C+4=0x10 ---- > = 306D_0010h
PCIE_PHY_CMN_REG05 306D_0000h base + 20h offset = 306D_0020h --- > should be : 0x10+4=0x14 ---- > = 306D_0014h
PCIE_PHY_CMN_REG06 306D_0000h base + 24h offset = 306D_0024h --- > should be : 0x14+4=0x18 ---- > = 306D_0018h
PCIE_PHY_CMN_REG07 306D_0000h base + 28h offset = 306D_0028h --- > should be : 0x18+4=0x1C ---- > = 306D_001Ch
.....
please pay attention to these registers, their suffix digits are hexadecimal.PCIE_PHY_CMN_REG1x should be PCIE_PHY_CMN_REG(1x16+x), for example:
PCIE_PHY_CMN_REG15 is PCIE_PHY_CMN_REG21, it's address should be : 306D_0000h base + 0x54 offset = 306D_0054h (0x54 is the hexadecimal of 21x4=84D)
[Additionally]
Confirmed with internal team, In pcie driver, registers' address are all correct, don't worry!
Thanks!
Regards,
weidong
I'm grateful for your response.