PCIe Reference Clock design

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PCIe Reference Clock design

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eishishibusawa
Contributor III

Dear Sir

Please tell me about the PCIe Reference Clock design of i.MX6DL.

I referred to SPF-27417_C5, IMX6DQ6SDLHDG Rev.3 and HW_Design_Checking_List_for_i.MX6DQP6DQ6SDL_Rev3.1.

SPF-27417_C5

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IMX6DQ6SDLHDG Rev.3 (P21)

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HW_Design_Checking_List_for_i.MX6DQP6DQ6SDL_Rev3.1

PCIe reference clock solution which provided by CLKx_N/P of i.MX6 chip can't pass PCIe Gen2 compliance test.  Recommend using external PCIe 2.0/3.0 clock generator with 2 HCSL outputs solution. One clock channel connect to i.MX6 as a reference input, please click Ref14 for reference circuit. Another clock channel should connect to PCIe connector, please contact generator vendor for detailed design guide.

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Q1.

Which is the most recommended design?

 

Best Regards,

Eishi SHIBUSAWA

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igorpadykov
NXP Employee
NXP Employee

Hi Eishi

recommended to use option provided with HW Design Checking List

and external generator.

Best regards
igor
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