Hello Eyal,
In EP's system, EP can access the reserved ddr memory (default address:0x40000000) of PCIe RC's system, by the interconnection between PCIe EP and PCIe RC. So I don´t see a problem.
Here is a link of a validation
i.MX6Q PCIe EP/RC Validation System
Have a great day,
Jaime
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------