Looking at the schematics for the MEK, it appears that only PCIE_CTRL0 pins are routed to the M.2 connector and PCIE_CTRL1 pins are instead routed to the B2B connector. If I've understood correctly, this means a device connected via the M.2 interface will only be accessible through the PCIE 0 (A) instance.
Is that correct? If so, how could I go about testing PCIE 1 (B)? Assume using NXP Linux kernel lf-6.1 with hsio-cfg set such that one lane each of phyx2 is assigned to PCIE instances 0 and 1.
On a related topic, I'm not able to find a schematic for the MCIMX8-8X-BB base board. Would appreciate being pointed in its direction.
