PCI-E Loopback Mode

[harrytan]

Hi,

I am using iMX6 Solo processor and I want to have signal sent out through PCI-E Tx lane get loopback to the Rx lane. This means that Tx and Rx lanes should have the same signal. Is this done by setting the bit 2 (Loopback_Enable) of Port Link Control Register (PCIE_PL_PLCR)? Thanks.

[Pavan_chate]

Hi harrytan,

could you please explain here the procedure how you did enable the loopback and all using code warrior? I need to check the loopback in PBL mode using code warrior.

Thanks and regards,

Pavan

[Pavan_chate]

Hi ,

I am also trying to enable the loopback of bit 2. I am using LX208A  and I need to enable it by using code warrior in PBL mode.
could you please explain the detailed procedure that how you have enabled the loopback from starting onward?

[igorpadykov]

Hi Harry

yes this bit is used as part of Local PIPE Loopback procedure usually used

during production test. NXP software BSPs do not use this procedure.

Best regards
igor
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[harrytan]

Hi Igor,

Do you have any thought on this? Thanks.

Regards,

Harry

[igorpadykov]

Hi Harry

please look at IP vendor documentation

DesignWare Dual Mode Controller IP for PCI Express 

Best regards
igor

[harrytan]

Hi igor,

I have enabled the Loopback_Enable bit and did not get the same signal on both Tx and Rx lanes. The data is sent from a FPGA to the iMX6 processor (Tx lane of FPGA to Rx lane of processor) and I probed on Tx lane of processor using oscilloscope. I expect to get the same signal on both lanes. 

I further read bit[54] (mac_phy_txdetectrx_loop PIPE receiver detect/loopback request) of DEBUG 1 (PCIE_PL_DEBUG1) register and this bit is '0'. Does this mean that the PHY did not get loopback request? Please advice, thanks.