Open Drain IO Configuration

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Open Drain IO Configuration

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sahilnayak
Contributor I

Hello NXP Team,

We are using custom hardware based on i.MX8M processor.

We are facing issue with SW_PAD_CTL_PAD_SD2_CD_B SW PAD Control register (IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B).

We are setting bit 5 (ODE) as 1 and bit 6 (PUE) as 0. We have added 100K external pull up resistor with 3.3V.

As per our understanding when this IO is driven low in output mode, it would be high as we have added 100K pull up resistor. When the IO is driven high in output mode, it would be be low.

But this is not happening. Please help us to confirm if any other configuration is required to be done other than mentioned above. 

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sahilnayak
Contributor I

Hi Team,

Any update on this?

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