Network clock (SRCK) not seen

[yehudastern]

Hi,

I'm working with i.MX6 connected to 2 codecs through SS1 & SS2 in I2S master mode.

Both of their clocks are originated from PLL4 (688.128 MHz), their SSI's sys clocks = 12.288 MHz, and their serial BCLKs = 1.536 MHz.

I wanted to connect the codecs' MCLKs, through CPLD, to SSI1_CLK and SSI2_CLK.

Both SSIx_CLKs can be routed to CLKO2 (by setting CCM_CCOSR accordingly) but not simultaneously.

On the other hand, connecting both MCLKs to the same SSIx_CLK causes phase shift problems in the codecs.

So I figured I'll connect the second MCLK through CPLD to the respective network clock (SRCK), which is AUD4_RXC.

In order to do that I set both TXDIR and SYS_CLK_EN to 1 (in SSI2_STCR and SSI2_SCR registers), but nothing appeared on AUD4_RXC (please refer to Figure 61-22 in i.MX6 RM).

Any suggestions why?

i.e.  I've set DISP0_DAT19 pin in IOMUX to AUD4_RXC instead of GPIO_5_13 (PCIE_RST).

     And I also set that pad to CMOS output: 

__raw_writel(0x1F0F1, IOMUXC_SW_PAD_CTL_PAD_DISP0_DAT19);

// PU=22K, Open Drain disabled (CMOS output), Speed=Max

BR,  

[igorpadykov]

Hi Yehuda

AUD4_RXC should be appropriately configured using AUDMUX

for routing  SSI1,2 SRC, as AUDMUX port 1,2 connected to SSI1,2.

Best regards

igor

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[yehudastern]

Hi Igor,

This was already done.   In file: board-mx6q-xxx.h,  I added:

MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC,

instead of the following line, which I marked as a comment:

//	MX6Q_PAD_DISP0_DAT19__GPIO_5_13,   /* PCIE_RST */

Here's the configuration of the 2nd codec (SSI2, port7, and AUD4):

static struct mxc_audio_platform_data ext_wm8962_data = {

  .ssi_num = 2,

  .src_port = 7,

  .ext_port = 4,

  .hp_gpio = -1,

  .hp_active_low = 1,

  .mic_gpio = -1,

  .mic_active_low = 1,

  .init = mxc_wm8962_init,

  .clock_enable = wm8962_clk_enable,

};

As mentioned above, I can route and measure SSI2_CLK (12.228MHz) to CLKO2, but apparently not to SRCK (AUD4_RXC).

BR,

Yehuda

[igorpadykov]

Hi Yehuda

suggest to printf AUDMUX/CCM registers or attach jtag

then check them.

Best regards

igor

[yehudastern]

Hi Igor,

This was already done.   I still have no idea why SSI2_CLK (12.228MHz) doesn't appear on SRCK (AUD4_RXC).

FYI, The problem was solved as follows:

The 1st codec's MCLK is connected to SSI1_CLK which is routed to CLKO1.  This codec bypasses its internal PLL.

The 2nd codec's MCLK is connected to BCLK (1.536 MHz) through CPLD.   This codec uses an internal PLL (with K=32.0, R=2, P=1).

This solution is acceptable as shown in TI's SLAA469, page 4 (Audio Serial Interface Configurations for Audio Codecs), and solved all the problems.

BR,

Yehuda