Need continuous BCLK?

[sparkyee]

Hi,  

    I am designing a product using the iMX6ULL. I need a clock to run my FPGA and cannot use

CCM Clock 1 or 2 since I am using SD card port 1 and I need the JTAG port operable. I am

thinking of using EIM "BCLK" and have found the "CONT_BCLK_SEL" bit in the EIM_WCR register.

There seems to be a lot of discussion in the community whether BCLK can function like one of the

CCM_CLK, this is possible? Will it work for my MCIMX6Y2CVM08AB part? I would like to test this

signal on my Freescale iMX6ULL-EVK and would also like to know how to change the UBOOT/ LINUX

software to accomplish this function from startup? If "BCLK"  is not continuously possible can you suggest

any other means of getting a continuous clock for the iMX6ULL part?

Thanks for reading and helping!

Larry

[weidong_sun]

Hello Larry,

see below, please!

(1) About EIM_BLCK

yes, the clock can be configured as continous in register EIM_WCR

more detailed information ,see reference manual, please!

(2) Suggestion on clock for your FPGA's working clock

--- provided by CPU

   The better choice is to get clock from CCM_CLKO1 & CCM_CLKO2.

--- Using external clock

   probably FPGA requires higher precision clock, From a technical point of view, you can choose to meet the requirements of OSC or crystal, which has no risk.

(3) Signal transmission synchronous clock

If your FPGA is connected to EIM interface and use SYNC mode, it is no problem to use BLCK for FPGA.  It is not recommended that you use BCLK as the working clock of FPGA.

Have a nice day!

BR,

weidong