Memory Issue in i.MX 6SoloX cortex M4

[nagaprasadvasam]

Hi Every One,

   I am Working on imx6solox sabre-sd Board,running cortex-m4 with FREERTOS and cortex-A9 with Linux. my Rtos Application for cortex-m4 exceeding 32kb memory limit for m4,can any one help me regarding how to increase code and data segment memory range for cortex-m4 and changes needed for linux addresses on cortex-A9.

Thanks & Regards,

NagaPrasad.

[Yuri]

Hello,

   Please refer to Table 2-2 (CM4 memory map) of i.MX 6SoloX  Reference Manual, Rev. 3, 07/2018,
 regarding available for CM4 memory. Note, DRAM MMDC memory is common for CA9 and CM4. 

https://www.nxp.com/webapp/Download?colCode=IMX6SXRM 

Regards,

Yuri.

[nagaprasadvasam]

Hi Yuri,

Thanks for ur reply,

i tried by using memory according to table in reference manual,i have edited linker file for ddr RAM as well as qspi.but there seems to be no change,can you please suggest some solution to work with cortex-m4 with peripheral functionality as expected with modification of Ram memory region.

[Yuri]

Hello,

  Do You use Linux on CA9?

How  CM4 code is loaded and run?

How memory is allocated between CA9 and CM4?

Regards,

Yuri.

[nagaprasadvasam]

Hai,

Yes i am running Linux on A9 & code is running through u-boot using ddr memory.

Regards,

Prasad.

[Yuri]

Hello,

  The DDR memory for CM4 should be reserved, as shown, for example in 

"reserve_m4_memory.docx"

https://community.nxp.com/docs/DOC-335105

Regards,

Yuri.