Maximum LPSPI frequency

[stefano-quantic]

I'm using iMXRT1176 and MCUXpresso IDE (v11.8.0 [Build 1165] [2023-07-26]).

The documentation is unclear about the maximum frequency for the LPSPI clock.
The datasheet ("IMXRT1170IEC", Rev. 5, 01/2024) has table 84, which states that the maximum Frequency of operation (fSCK) is fPERIPH/2, which is clear enough.
However, the datasheet never defines what fPERIPH is, nor does it give any range for it.
Also, table 84 has note 1, regarding fSCK, which says that "Absolute maximum frequency of operation (fop) is 30 MHz".
This seems to be saying that the LPSPI clock root must be <= 60MHz (so that fSCK <= 30MHz), unless I use a divider higher than the minimum one (/2).

However, Config Tools says that the limit for the clock root is 135MHz (so, fSCK <= 67.5MHz). This can be verified in Config Tools by setting a clock root frequency higher than that – an error like the following will be shown in the "Problems" view:
====
Issue: The output frequency must be lower than or equal to: 135 MHz
Level: Error
Type: Tool problem
Tool: Clocks
Origin: Clocks: BOARD_BootClockRUN
Resource: CCM.LPSPI1_CLK_ROOT
Information: The output frequency must be lower than or equal to: 135 MHz (See constraint 1)
====

The 135MHz limit doesn't appear anywhere in the datasheet.

What is the actual limit for the LPSPI clock?

Is it correct that the clock root can be as high as 135MHz, but that in this case I need a higher divider, so that fSCK is <= 30MHz anyway?

Also: Config Tools, in the "Peripherals" view, let me configure an LPSPI with a 132MHz clock root, and a baudrate of 66MHz (resulting in a /2 divider), without raising any errors.
The FSL library has no objections either: LPSPI_MasterInit(), which then calls LPSPI_MasterSetBaudRate(), accepts these parameters (132MHz source clock, 66MHz baudrate) without complaining.

[EdwinHz]

Hi @stefano-quantic,

Even though the clock root for the LPSPI module supports higher frequencies, Note 1 of the datasheet sates that the module maximum frequency of operation for the fSCK is 30MHz, so the frequency for the peripheral (fperiph) must be <=60MHz for proper functionality of the module. In other words, setting the clock root to a higher frequency might result in unexpected behaviors for the LPSPI module, so the recommendation is to maintain fperiph to <=60MHz to ensure proper functionality of the peripheral.

BR,
Edwin.

[stefano-quantic]

Hi Edwin, thanks for your reply.

What if I set the clock root to 120MHz, and a prescaler and/or divider equal to /4, such that I get 30MHz on the pins?

Would this be guaranteed to work?

[EdwinHz]

Hi @stefano-quantic,

This should be OK. The restriction is based on the frequency of the SCK (fSCK), so as long as fSCK is <=30MHz, the module will work.

BR,
Edwin.