MX8M plus ECC on OCRAM n L1 L2 cache

[Jagmevada]

I m planning to use MX8m plus for application where SER is not acceptable, can somebody confirm if this device has ECC on its OCRAM (868kb) and ECC on L2 cache (512kb) as some datasheet n online block diagram are confusing this specification, also pl confirm if any ECC or parity feature there for L1 chache 

[jamesbone · Accepted solution]

ECC on OCRAM/TCM it is enabled by default.    L1 Cache has parity bit for 1-bit Error, since this is part of the archicterure of the ARM Cores, but it is not enable by default,  for cheching settings you need to look into the ARM Core Documentation. 

• ACTLR_EL1 (Auxiliary Control Register):
  • Controls parity and ECC features.
  • Bits related to parity:
  • L1IPE (bit 19): Enable parity for L1 instruction cache.
  • L1DPE (bit 20): Enable parity for L1 data cache.

[Jagmevada]

Further studying mx8mp documents, for OCRAM ECC, I could find single document mentioning about ECC details on OCRAM, not even in mx8mp ref manual. Could you please provide details, where I can find register details of ECC OCRAMs, how can we inject bit error to OCRAM to see ECC performance,  also want to log ECC errors (SER), is there any interrupt to trigger when Error occured? Pl help on this, we cannot use device if ECC is not there in silicon revision.

[jamesbone]

We can confirm that, the i.MX8M Plus does support ECC on OCRAM and L2 cache, but not on L1 cache. The ECC reference in the datasheet includes software-accessible SRAMs like OCRAM and TCM.

To avoid any more confusion the NXP product page has the mistake with the 768 KB OCRAM with EC,  the correct number it is in the Datasheet with the 868 KB OCRAM.

This ECC applies to the internal software-accessible SRAMs like it was already mention  this includes OCRAM and TCM used by CHiFi4 DSP and Cortex-M.

[Jagmevada]

Thank you so much for confirmation. just last clarification on ECC, do we need to enable ECC on OCRAM/TCM or it is enabled by default. Also, does L1 caches (data/instr for M7 MCU and A53 cores) has parity bit for 1-bit error detection?, if so it is enabled by default?

[JorgeCas]

Hello,

According to datasheet block diagram ECC is supported in 512 KB L2 Cache and x32 LPDDR4/DDR4.

Best regards.

[Jagmevada]

On first page of datasheet,

"High industrial system reliability for safety is leveraged by DRAM Inline ECC as well as ECC support on internal software-accessible SRAMs." 

Is it talking about OCRAM/TCM used with internal HIFI4 and MCU ?

Also on product main page on NXP website https://www.nxp.com/products/i.MX8MPLUS, it is mentioned 768 OCRAM with ECC, but datasheet says 868kB OCRAM (no mention of ECC)

Also in attached product brief pdf it is mentioned it has ECC on OCRAM. 

It is essential to have low SER for application for which we are planing to use this device. ECC would greatly enhance effective SER performance, and this device has all functions which we are looking for, so please could you reconfirm whether it has ECC on OCRAM or not. also pl confirm if L1 cache has parity (single bit error detection) bit or not.