Thanks Sun,
We are using PMIC DA9053, and are still working on the idle state current consumption on Android system.
I believe our platform is DVFSC functioning, we measured the change current change of VDDGP. At Idle state, VDDGP is only 2mA. At operating state, VDDGP can be over 400mA. However there is a few question about reducing the power consumption.
1. the current of VCC_1V3 is 116mA at idle state and 200mA at operating state. Can the current of VCC_1V3 be reduced?
2. In the file MX53_wp.c, I believe the following structure are related to DVFSC
static struct dvfs_wp dvfs_core_setpoint_ces[] = {
{33, 25, 33, 10, 10, 0x08}, /*1GHz*/
{30, 18, 33, 20, 10, 0x08}, /* 800MHz */
{25, 8, 33, 20, 10, 0x08}, /* 400MHz */
{28, 8, 33, 20, 30, 0x08}, /* 400MHz, 133MHz */
{29, 0, 33, 20, 10, 0x08},}; /* 400MHz, 50MHz. */
and
static struct cpu_wp cpu_wp_ces[] = {
{
.pll_rate = 1000000000,
.cpu_rate = 1000000000,
.pdf = 0,
.mfi = 10,
.mfd = 11,
.mfn = 5,
.cpu_podf = 0,
.cpu_voltage = 1250000,},
{
.pll_rate = 800000000,
.cpu_rate = 800000000,
.pdf = 0,
.mfi = 8,
.mfd = 2,
.mfn = 1,
.cpu_podf = 0,
.cpu_voltage = 1100000,},
{
.pll_rate = 800000000,
.cpu_rate = 400000000,
.pdf = 0,
.mfi = 8,
.mfd = 2,
.mfn = 1,
.cpu_podf = 1,
.cpu_voltage = 950000,},
};
I am not sure what is the usage of this two structures.
cpu_wp_ces changes the PLL setting, when and how the setting be used?
dvfs_core_setpoint_ces changes the DVFSC threshold setting, how does the setting be used?