Low frequency screens initialization in U-boot for splash screen

[alexandrspivac]

Hellow

I am using "i.MX6Q" SOM 

I make some modifications in u-boot

I am using version v2015.04 

I have to initialize screens in U-boot and put a splash screen on them.

I added support for small screens. Derived clock from PLL2 PFD0  to pll5. Added configuration for dividers of pll5 in board code file. Added support of pll5 clock to "ipu_common.c" code file and put this clock to ldb_clk[0].rate and ldb_clk[1].rate Some code of this:

static unsigned long get_pll5_clk_rate(void)
{
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
int reg;
int post_div_select = 1;
int div_select;
int num;
int denum;
unsigned long ret;

reg = readl(&ccm->analog_pll_video);
//post_div_select = reg & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT >> BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
switch ((reg & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT) >> BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT) {
case 0:
post_div_select = 4;
break;
case 1:
post_div_select = 2;
break;
case 2:
post_div_select = 1;
break;
default:
break;
}
div_select = reg & BM_ANADIG_PLL_VIDEO_DIV_SELECT;
reg = readl(&ccm->analog_pll_video_num);
num = reg & BM_ANADIG_PLL_VIDEO_NUM_A;
if ( num & (1<<29) ) num |= 0xC0000000;
reg = readl(&ccm->analog_pll_video_denom);
denum = reg & BM_ANADIG_PLL_VIDEO_DENOM_B;
ret = ( unsigned long ) (24000000.0*((float)div_select+(float)num/(float)denum)/(float)post_div_select);
#ifdef DEBUG
debug("Function %s post_div_select = %d\n", __func__, post_div_select);
debug("Function %s div_select = %d\n", __func__, div_select);
debug("Function %s num = %d\n", __func__, num);
debug("Function %s denum = %d\n", __func__, denum);
//debug("Function %s divider = %9.6f\n", __func__, divider);
debug("Function %s pll5 clock = %lu\n", __func__, ret);
#endif
return ( ret );
}

in int ipu_probe(void)

ldb_clk[0].rate = get_pll5_clk_rate()/7;
ldb_clk[1].rate = ldb_clk[0].rate;

I successfully initialize this my screens and have a splash screen :

struct display_info_t const displays[] = {{
.bus = -1, 
.addr = 0, 
.pixfmt = IPU_PIX_FMT_RGB24, 
.detect = detect_display_board_obc,
.enable = enable_lvds_obc, 
.mode = {
.name = "HVGA-OBC",
.refresh = 60,
.xres = 480,
.yres = 272,
.pixclock = MHZ2PS(9), 
.left_margin = 2, 
.right_margin = 2, 
.upper_margin = 2, 
.lower_margin = 2, 
.hsync_len = 41,
.vsync_len = 10, 
.sync = FB_SYNC_EXT , 
.vmode = FB_VMODE_NONINTERLACED 
} }, {
.bus = 0, 
.addr = -1, 
.pixfmt = IPU_PIX_FMT_RGB24, 
.detect = detect_display_board_vt600,
.enable = enable_lvds_vt600, 
.mode = {
.name = "WVGA-VT600",
.refresh = 60, 
.xres = 800,
.yres = 480,
.pixclock = MHZ2PS(30), 
.left_margin = 88, 
.right_margin = 40,
.upper_margin = 32,
.lower_margin = 13, 
.hsync_len = 48, 
.vsync_len = 3,
.sync = FB_SYNC_EXT,
.vmode = FB_VMODE_NONINTERLACED
} } };

After some resets of u-boot in some cases screen not initialized properly and screen white with color lines.

U-boot copy kernel and device tree to ram and hang.

After some debugging, I founded an endless loop in the file "ipu_disp.c" :

do {
reg = __raw_readl(IPUIRQ_2_STATREG(irq));
} while (!(reg & IPUIRQ_2_MASK(irq)));

I understand that initialization was not properly but cannot find what cause this.

Someone can help me?

 All Regards,

Alex

[igorpadykov]

Hi Alex

example of low frequency initialization can be found on

https://community.nxp.com/message/833716?commentID=833716#comment-833716 

uboot logo patches:

https://community.nxp.com/docs/DOC-98109 

Best regards
igor
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[alexandrspivac]

Hi Igor 

I saw all of this posts before I started to develop my implementation.

In this patches video using pll5 with u-boot version 2017 and up for kernel 4.9 and up.

I'm using u-boot v 2015.04 for kernel 4.1.15 that received in BSP.

I cant use most of this code in my project.

All patches for version 2017 and up don't use a driver of ipu from directory /drivers/video/... they used new implementation. 

All of this implementations is for  1024x768 VLDS screens only and minimum pll5 clock 

My screens smaller than all these screens.

I founded that this patch support uses: #define PLL5_FREQ_MIN 650000000  I need smaller frequency for my project ( my minimal clock is 63MHz and after dividing on 7 bit in a word of LVDS it will be 9MHz).

I already running screen on clock 63MHz (9MHz pix_clk) and 210MHz (30MHz pix_clk).

It's new implementation but I have some bug in ipu driver implementation ( mxc_ipu3_fb.c ipu_common.c ipu_disp.c) - sometime after reset of u-boot some of the registers not configured correctly and screen not working. In this case if I let it continue to load kernel of linux u-boot load kernel to ram and try to ipuv3_fb_shutdown() in file cpu.c and enter to endless loop because registers of DMA not configured properly.

Do you know someone who developed ipu driver implementation?

All regards,

Alex

[igorpadykov]

Hi Alex

one can try help of NXP Professional Services:

NXP Professional Services|NXP 

Best regards
igor
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