Limited PLL options for setting up LVDS pixel clock on IMX8MP

[rbeims]

When trying to setup the parameters for a custom LVDS display on the IMX8MP native LVDS (ldb) interface, we noticed that it's not possible to achieve the needed 60MHz Pixel Clock:

&panel_lvds {
 status = "okay";
 backlight = <&backlight_lvds>;
 data-mapping = "vesa-24";
 compatible = "panel-lvds";
 width-mm = <199>;
 height-mm = <112>;
 panel-timing {
 clock-frequency = <60000000>;
 hactive = <1280>;
 hback-porch = <32>;
 hfront-porch = <32>;
 hsync-len = <44>;
 vactive = <720>;
 vback-porch = <9>;
 vfront-porch = <9>;
 vsync-len = <5>;
};

    video_pll1_ref_sel                1        1        0    24000000          0     0  50000
       video_pll1                     1        1        0  1039500000          0     0  50000
          video_pll1_bypass           1        1        0  1039500000          0     0  50000
             video_pll1_out           2        2        0  1039500000          0     0  50000
                media_ldb             1        1        0   519750000          0     0  50000
                   media_ldb_root_clk       1        1        0   519750000          0     0  50000
                media_disp2_pix       1        1        0    74250000          0     0  50000
                   media_disp2_pix_root_clk       1        1        0    74250000          0     0  50000
                media_mipi_phy1_ref       0        0        0    47250000          0     0  50000

Looking through the code, we can see that the pixel clock options seem to be limited at the driver (drivers/gpu/drm/imx/imx8mp-ldb.c):

static int                                                                                                                                                     
imx8mp_ldb_encoder_atomic_check(struct drm_encoder *encoder,                                                                                                   
                                struct drm_crtc_state *crtc_state,                                                                                             
                                struct drm_connector_state *conn_state)                                                                                        
{                                                                                                                                                              
        struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
...
        /*                                                                                                                                                     
         * Due to limited video PLL frequency points on i.MX8mp,                                                                                               
         * we do mode fixup here in case any mode is unsupported.                                                                                              
         */                                                                                                                                                    
        if (ldb->dual)                                                                                                                                         
                mode->clock = mode->clock > 100000 ? 148500 : 74250;                                                                                           
        else                                                                                                                                                   
                mode->clock = 74250; 
                                                                                                                                                               
        return 0;                                                                                                                                              
}

However, if we bypass this check (commenting these lines out) and setup a different root clock for the chain we're able to achieve the desired pixel clock:

    video_pll1_ref_sel                1        1        0    24000000          0     0  50000
       video_pll1                     1        1        0   960000000          0     0  50000
          video_pll1_bypass           1        1        0   960000000          0     0  50000
             video_pll1_out           2        2        0   960000000          0     0  50000
                media_ldb             1        1        0   480000000          0     0  50000
                   media_ldb_root_clk       1        1        0   480000000          0     0  50000
                media_disp2_pix       1        1        0    60000000          0     0  50000
                   media_disp2_pix_root_clk       1        1        0    60000000          0     0  50000

The code that I showed above is from linux 5.4 but I already checked on 5.15 and the check for the pixel clocks is still there.

Considering this, I would like to ask:

What is the reason for this limitation? It seems that the hardware supports other options than 75Mhz or 150Mhz and this is also stated in the Reference manual:

Thank you in advance for the help,

Rafael

[joanxie]

the reason I think already post in the code already, because limited video PLL frequency points on i.MX8mp, so not all of lvds clock can be supported, if can be supported, just remove the code as you did though the code uses fixed clock as default

[fd]

just remove the code as you did though the code uses fixed clock as default

I would expect the driver code to be fixed by NXP. The current driver just set a fixed clock value while the hardware limitation is on the maximum one, to me this is just a bug. Am I misunderstanding something?

[joanxie]

what pixel clock LVDS do you support? still 60Mhz?

[fd]

In general we do need software support for any pixel clock that the HW can provvide, 60MHz is just a specific case we stumbled across.

We are not talking about a product with a specific display panel connected here, but on a generic product that should be able to be connected to any panel that the HW supports with no arbitrary limitation from the SW.

[joanxie]

this clock is from PLL is fixed in the current bsp, if customer use different clock, they need to change the PLL source from the clock driver source code, and couldn't support any clock customer wants

https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/clk/imx/clk-pll14xx.c?h=lf-5.10.y

static const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = {
PLL_1443X_RATE(1039500000U, 173, 2, 1, 16384),
PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
PLL_1443X_RATE(594000000U, 198, 2, 2, 0),
PLL_1443X_RATE(519750000U, 173, 2, 2, 16384),
PLL_1443X_RATE(393216000U, 262, 2, 3, 9437),
PLL_1443X_RATE(361267200U, 361, 3, 3, 17511),
};

customer wants to support clock besides of 74.25 and can source from imx_pll1443x_tbl, they just comment the code which fixed the clock to avoid unsupported mode

[fd]

Am I understanding correctly that the official answer from NXP is that the LVDS clock can be configured only changing the pll clock source from the source code? This is at the same time disappointing and unexpected.

Do you have any plan to improve this to make this configurable?

[joanxie]

I checked the reference manual and current bsp, if you need more pixel clock support, you can add by yourself, I wrote a document for you, maybe you can refer to this, because this clock's range is too wide, so the R&D team just add limited clock in the table

"https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/different-lvds-support-on-imx8mp/ta-p/15..."

[joanxie]

this depends on soc design, I don't think development team has this plan to change