Layout Design Guide Line for LPDDR4 on i.MX8QX

[tanno_yoshihiro]

Hello,

Now, we are designing our evaluation board circuit using iMX8QX.
So we want to know the following specification for LPDDR4 Layout Design Guide Line.

1.Line Length Difference (Differential Pair P/N, CK/DQS)
2.Line Length Difference (Single - ended, CS/CKE/DMI/CA/DQ)
3.Space between Differential Pair and Other Traces
   - CK_t/c to CAx, CS_n
   - CK_t/c to CKEx
   - CK_t/c to DQSx_t/c
   - DQS_t/c to DQ
   - DMI to DQ
4.Characteristic Impedance (Z0)
5.Differential Impedance (Z0_diff)

Thanks a lot
Yoshihiro

[Okiann]

Hi Yuri,

May I have a copy of the guide doc in pdf? Could you send me through email if it is available to send. Thank you.

[Yuri]

Hello,

   I've sent You reply directly.

Have a great day,

Yuri

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[tiagoborth]

Hi Yuri, it would be possible share the same information regarding iMX8QX + LPDDR4 line impedances?

[Yuri]

@tiagoborth 

https://community.nxp.com/t5/Nominate-to-Knowledge-Base/LPDDR4-line-impedance-on-i-MX8QX/ta-p/115322...

[hrudaynath]

Hi Yuri 

can you please send this document to me please 

hrudaynath.chaudhari@cummins.com 

[sergeyserg]

Hello Yuri,

Now I am doing pcb design with iMX8MMini and I have got the same questions about layout LPDDR4 only for iMX8MMini. Could you send me these layout applications LPDDR4 for iMX8MMini?

Thanks

Serg.