LVDS panel display corruption

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LVDS panel display corruption

4,931 Views
saurabh206
Senior Contributor III

Hi,

We are using custom hardware based on IMX6q.

LVDS panel is connected to hardware and some times we are getting display corruption.

How we can fixed this issue? What could be the reason behind this?

Thanks

Saurabh20140303_091834.jpg20140303_091907.jpg

14 Replies

1,180 Views
saurabh206
Senior Contributor III

Hi,

Any Valuable guideline from Freescale Team?

Thanks

Saurabh

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1,180 Views
jamesbone
NXP TechSupport
NXP TechSupport

I would said that the issue it is timing related, you can review the fb structure that it is according to your LVDS display. I would recommend to measure the pixel clock to see it is according to the LVDS.  Can you share your settings? Another way to review it is to slow down the resolution of the display to see if it is corrected.


Have a great day,
Jaime

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saurabh206
Senior Contributor III

Hi,

Thanks for taking interest and replay for this issue.

This issue occurs randomly. After reboot or suspend resume this issue disappear and visa verse.

I am using 1080p display Panel.

static struct fb_videomode ldb_modedb[] = {

     "LDB-1080P60", 60, 1920, 1080, 6800,

     128, 138 ,

     22, 3,

     80, 4,

     0,

     FB_VMODE_NONINTERLACED,

     FB_MODE_IS_DETAILED,},

};

And pll2_pfd_352M is used as clocking source for the LDB pixel clock,

Is It possible LDB pixel clock (pll2_pfd_352M ) has some jitter ?

Thanks

Saurabh

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saurabh206
Senior Contributor III

Hi,

I have measured the clock signal

- LVDS0_CLK_P signal and it is always vary between 69.9 MHz to 73.3 MHz.

     According to me it should be stable at any one value according to rounding clock rate. What could be wrong in this case?

In LDB split mode how the LVDS0_CLK_P and LVDS1_CLK_P generated from IPU_DI0_CLK?

When i have display corruption difference between LVDS0_CLK_P and LVDS1_CLK_P is approx 2 Hz, And for the proper picture this difference is between 0.2 Hz.

-      Ideally this both clock LVDS0_CLK_P and LVDS1_CLK_P should be same because it is generated from same clock source.

Any Valuable comment from Freescale team?

Saurabh

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RodBorras
NXP Employee
NXP Employee

Saurabh,

Could you please check bit 17 of the IPUx_DI0_GENERAL register and make sure it is not the "Incorrect Setting" here below:

Untitled.png

Regards,

Rod.

1,179 Views
boudewijn-ame
Contributor II

Hi Rod,

I have the same issue and i have solved it with your settings. Thank you. I would like to give some more information about what i saw. First i made a .bmp picture with only one pixel RGB colour = 127, 127 and 127. Then I send the whole picture to the screen using the following linux command:

dd if=/media/sda1/test.bmp bs=138 skip=1 > /dev/fb (The test image is a 1280x800 RGB565 bitmap file)

We then saw a shift in pixels:

IMG_0235.JPG.jpg

When setting the following setting: addr 0x02640008 to 0x00020001 (was 0x00010000), the problem was fixed.

Below a measurement of the LVDS signals, CLK and RX1:

Red and blue are the incorrect image with shifted bits. Pink is the correct image.

lvds_good.png

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yuefengzhu
Contributor I

Hello, Thank you for sharing you info, I got somehow similar problem. Could you guys kindly share with  me how to set or read the register values for imx6?  How do we check and change the value of the following registers?

IPU_DI0_GENERAL 

IPU_DI0_BS_CLKGEN0

IPU_DI0_BS_CLKGEN1

Thank s a lot

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RodBorras
NXP Employee
NXP Employee

Cool. Thanks for sharing!

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saurabh206
Senior Contributor III

Hi,

Rod

Register values are as follow.

IPU_DI0_GENERAL            --> 0x00300000;

IPU_DI0_BS_CLKGEN0      --> 0x00000010;

IPU_DI0_BS_CLKGEN1      --> 0x00010000;

Regards

Saurabh

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RodBorras
NXP Employee
NXP Employee

Hi Saurabh,

I have another customer with a similar problem. He is running Android, and it seems you are too.

The following patch seems to work for them. Would you please give it a try too?

Thanks,

Rod.

1,178 Views
everlook
Contributor I

We are experiencing the same issue driving an LVDS panel. The patch (ENGR00304402) appears to be for the 3.0 kernel. Is there an updated patch the the 3.10.17 GA release?

Thanks,

Jeff

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everlook
Contributor I

I was able to patch the 3.10.17 GA FSL kernel (using the code above) and the LVDS is now working without issue. We are still testing but all looks good. It appears I can not attach files to this post so I'm not sure how I can post the patch.

Thanks,

Jeff

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saurabh206
Senior Contributor III

Hi,

Rod

I have applied the patch and there a improvement.

I will test for longer period of time and provide you update.

Thanks

Saurabh

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karina_valencia
NXP Apps Support
NXP Apps Support

jamesbone can you  continue with the follow up?

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