LVDS disabling DE sync signal

[digkleppe]

Hi,

Case: LVDS display on imx6 Solo Linux 3.14

The display sometimes gets out of sync. The LCD can work wit H-and Vsync or DE. The LCD datasheet says nothing about supplying all syncs.

We measured that all these signals are present in the LVDS data. We expected  that when the hsync-active,  vsync-active and de-active when not mentioned in the DTB these would be ignored. The corresponding  LVDS bits should be low (or high?).

We measured that all the signals are present. It seems that this is the reason for our troubles.

I found this post:     https://community.nxp.com/thread/302384

The H-and V sync cannot be disabled. How about the DE?

Dig

[digkleppe]

Hi Igor

Thanks for your reaction. In the meantime we found that our problems are likely caused by hardware.

The LCD is connected to a Solidrun SOM by short matched differential pair traces ( 61mm long) . 4 layer PCB with good groundlayer. We cannot imaginge what is going wrong.

The LCD works OK when connected to a VGA-LVDS board. We copied the timingparameters from this board. Still troubles with some boards/LCD's. Mostly not reproducable.

The VGA-LVDS board also produces all sync signals.  If we connect a LVDS to TTL converter board to our PCB we can measure the sync clk etc. All is Ok, so it is not caused by the imx.

Ideas welcome!

Dig

[digkleppe]

Update:

We noticed that the LCD was getting initialized 2 times: in the kernel and when the user (QT) program was started.  Both are needed. When the second init took place the LVDS signals dropped for a short time. In a trial-and-error way I have put a LVDS buffer between LCD and imx. Then no more problems. 

[igorpadykov]

Hi Dig

>The H-and V sync cannot be disabled. How about the DE?

it is the same, as all these signals are defined in ipu microcode (ipu_disp.c) producing

timings according to sect.4.11.10.6.1 IPU Display Operating Signals i.MX6DQ Datasheet

http://www.nxp.com/docs/en/data-sheet/IMX6DQCEC.pdf 

please check similar thread

How to change IMX53 VGA HSYNC from DI1_PIN7 to DI1_PIN4 -blog archive 

Best regards
igor
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