LPSPI3 Chip select is high continously

cancel
Showing results for 
Search instead for 
Did you mean: 

LPSPI3 Chip select is high continously

183 Views
yellapu_anishkh
Contributor II

Hi,

I am working on imx8 target, connected my LPSPI3 to ADC.

I have configured pins as shown below.

pinctrl_lpspi3: lpspi3grp {
fsl,pins = <
SC_P_SPI3_SCK_ADMA_SPI3_SCK   0x0600004c
SC_P_SPI3_SDO_ADMA_SPI3_SDO  0x0600004c
SC_P_SPI3_SDI_ADMA_SPI3_SDI      0x0600004c
SC_P_SPI3_CS0_ADMA_SPI3_CS0    0x0600004c
SC_P_SPI3_CS1_ADMA_SPI3_CS1    0x0600004c
>;
};

In my current setup, i am getting clock and data on MOSI, but chip select is continuously high. I want to change the pin configuration to pull down by default instead of pull up.

I am not able to find the SCU registers in Reference manual, please point me to the reference manual from where i can get these registers.

i want to understand the value assigned to "SC_P_SPI3_CS1_ADMA_SPI3_CS1    0x0600004c", how to make default configuration of CS1 low.

Tags (1)
0 Kudos
1 Reply

118 Views
igorpadykov
NXP TechSupport
NXP TechSupport

Hi Anish

polarity can be changed by bit PCSPOL register CFGR1, seems it is not

configurable via dts and changes may be applied in driver

spi-fsl-lpspi.c\spi\drivers - linux-imx - i.MX Linux kernel 

SCU registers are not available for users, it necessary to use APIs using

SCFW Porting Kit

Value assigned to "SC_P_SPI3_CS1_ADMA_SPI3_CS1 is pad configuration value

described in Chapter "IOMUXD" i.MX8QM Reference Manual.

Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

0 Kudos