LPDDR4 issue in i.MX8QXP custom SOM board and required RPA file

[sai_jyothi]

Hi,

I am using MT53E768M32D4DT-053 AIT:E LPDDR4 in my custom board and processor is used i.MX8QXP.

I am using the attached RPA file but i am getting below error. Debug log also attached for your reference, we got errors in this log also.

I checked with Micron, he has suggested to change in the register values, below is the details:

"Slightly tune VrefCA, VrefDQ, Drive Strength, ODT; Check tRFC compatible or not.

 All DRAM registers could be written from controller software: VrefCA is in DRAM register MR12, VrefDQ is in DRAM MR14; Write ODT is in DRAM MR11 and MR22, Read ODT is not in DRAM but in controller side registers; Read Drive Strength is in DRAM MR3, Write Drive Strength is not in DRAM but in controller side registers; Read latency RL and Write latency WL are in DRAM MR2."

Can you please provide the updated RPA file with respect to the Micron team feedback.

we need to resolve this issue immediately as the SOM board integration is blocked on this LPDDR4 issue.

Regards,

Jyothi.

[sai_jyothi]

Okay, thanks for your reply.

We have i.MX8QXP EVK with us and it has LPDDR4: MT53B768M32D4DT-062 AIT:B and we verified the custom board schematic with EVK schematic. both are same. Layout wise also we followed Micron suggested layout guidelines.

Can you provide the details which point we can consider related to this error "Error accessing SS = A35". Please suggest.

Is any NXP EVK is available with the exact LPDDR4: MT53E768M32D4DT-053 AIT:E

We checked with Micron also, he suggested to change in the register values in RPA file. Listed above.

Can you provide the updated RPA  file then as Micron requested we can try the DDR test.

[igorpadykov]

I can help to verify your RPA file settings, for that please provide (one can use for that

service request): ddr datasheet, board schematic (at least ddr part), processor full part number.

Best regards
igor

[sai_jyothi]

Hi Igor,

Thank you for response. I have attached LPDDR4 part datasheet and schematic for your reference.

Processor complete part number:PIMX8QX6AVLFZAB (Image also attached for reference).

Please provide the RPA file.

Regards,

Jyothi.

[igorpadykov]

Hi Jyothi

please provide schematic with better quality, also what is voltage provided to VDDQ.

Best regards
igor

[sai_jyothi]

Hi Igor,

Please find the schematic with better quality.

VDDQ and VDD2 voltage is 1.1V.

Regards,

Jyothi.

[igorpadykov]

Hi Jyothi

feedback from internal team:

--------------------------------------

From your logs, I think you have connected a incorrect UART to SCU debug port and you should connect to A35 debug port. But from the SCU debug port, we found there was Exception in the end of SCFW. It may be caused by incorrect SCFW(mx8qx_scfw_download.bin or mx8qxb0_scfw_download.bin)  used in your DDR stress tester tool.

1. Which DDR stress tester tool did you use?

2. Which reference schematic did your customer use, validation board or mek board? 

3. Did your customer build the specific SCFW for their board?

4. Which Linux code base did your customer use?

--------------------------------------

Best regards
igor

[sai_jyothi]

Hi Igor,

Is UART2 port of iMX8QXP is A35 debug port, confirm. If not, provide the port details.

UART details: I have connected 3 UART's (UART0, M40_UART0 & UART2) while doing DDR calibration test. Please confirm whether this UART's are correct or not.

I have attached the DDR stress tool which I used.

Can you provide the correct mx8qx_scfw_download.bin or mx8qxb0_scfw_download.bin files.

Reference schematic we used is :SPF-29683-C2

Please provide the boot setting details while doing DDR test. 

We have used NXP's default SCFW for the custom board, because we are using same LPDDR4 as EVK.

[sai_jyothi]

Hi,

I have attached SCU_UART_debug information image. We have not getting as expected in our custom board compared to EVK board.

Please provide the SCFM firmware loading procedure.

[igorpadykov]

Hi Jyothi

feedback from internal team:

--------------------------------------

As customer said, they follows the NXP MEK schematics in power and LPDDR4 design. Hence, we can conclude

1.  UART2 is the default A35 debug UART. There is no connection mistakes.

2. The default SCFW embedded in ER14 DDR tool is correct, no need to replace.

From customer's SCFW debug log, we can find there is hardware issue in their SOM board and A35 is not alive. 

--------------------------------------

So it is confirmed that this is hardware issue. If You have difficulties with board bring-up

may be recommended to proceed with help of NXP Professional Services:
https://contact.nxp.com/new-prof-svcs-sw-tech

Best regards
igor

[sai_jyothi]

Hi Igor,

Thanks for the reply..

From customer's SCFW debug log, we can find there is hardware issue in their SOM board and A35 is not alive. --- can you explain more on what kind of hardware issue you found, means component failure (if yes, which component it is Processor or LPDDR ) or any programming issue or any other issue.

Please describe more to proceed further.

Regards,

Jyothi.

[igorpadykov]

Hi Jyothi

log "Error accessing SS = A35" means there is no power on A35, probably due

to poor soldering of layout errors. So recommended to resolder chip and perform

x-ray board screening.

Best regards
igor

[sai_jyothi]

Hi Igor,

Thanks for the reply..

We measured the voltages at VDD_CPU & VDD_GPU, we got 0V instead of 1.1V. We measured in i.MX8QXP EVK also, I got 0V when initial power ON but after DDR test we got 1.1V on these power rails.

We connected all the power rails as per EVK board.

We verified the PMIC datasheet, these two power rails (VDD_CPU (SW4) & VDD_GPU (SW3)) are default will not power ON.

If we take EVK as reference, please provide how can i get these voltages.

We verified X-ray images also and found Okay, there is no solder issues we found.

Regards,

Jyothi.

[igorpadykov]

Hi Jyothi

how many boards are affected by this issue.

Best regards
igor

[sai_jyothi]

Hi Igor,

We have assembled 5 proto boards. We tested only one board.

To ensure the HW bring up, we connected VDD_CPU 1.1V power rail from EVK to our custom board VDD_CPU. Then we did DDR test first on EVK then we got 1.1V on VDD_CPU after that we tried the DDR test on Custom board and we got logs same as EVK and DDR stress test is successful.

As i mentioned in previous reply, In EVK also we got 1.1V after DDR test and it will be there until power OFF.

I have attached the EVK & Custom board logs for your reference, please check and confirm.

Can you please suggest with how we will get VDD_CPU & VDD_GPU voltage on our custom board without taking supply rail (VDD_CPU) from EVK board, any configuration is required or programming etc..

Regards,

Jyothi.

[igorpadykov]

Hi Jyothi

please test remaining 4 four boards.

Best regards
igor

[igorpadykov]

Hi Jyothi

from log "Error accessing SS = A35" there may be hardware issues, so first recommended to

check board using  i.MX 8QuadMax/i.MX 8QuadXPlus Hardware Developer’s Guide

Also i.MX8QXP MEK uses similar ddr part MT53B768M32D4DT, so one can try its settings.

Best regards
igor

[sai_jyothi]

Hi Igor,

I am referring the NXP EVK i.MX 8QXP CPU BOARD (SPF-29683-D6).

Can you please provide the measured impedance value at TP56 (VDD_DDRIO power rail) with respect to GND.

It is very urgent, please provide the details on priority.

Regards,

Jyothi.

[sai_jyothi]

Hi,

Can you provide the measured impedance value at TP56 (VDD_DDRIO power rail) with respect to GND. 

It is very urgent to confirm the assembly of the boards.