LPDDR2 on i.MX6DL

[elliottyang]

Hi All

I would like to use e.MCP(Kingston 08EMCP08-NL2CV100-C50) which is e.MMC 8GB + LPDDR2 8Gbit on our i.MX platform .

Freescale provides a table for the DDR3 and LPDDR2 pin mux mapping (IMX6SDLRM.pdf page.3904)

But I don't know what is the DRAM_BA0 and DRAM_BA1, does it mean DRAM_SDBA0 and DRAM_SDBA1?

Could anyone help me to check the schematic?

Thanks,

Elliott

[art]

Q. What is the DRAM_BA0 and DRAM_BA1, does it mean DRAM_SDBA0 and DRAM_SDBA1?

A. Yes.

I have checked the interconnection diagram of i.MX6 and LPDD2 on the schematic sheet you've provided, it is correct. To follow the JEDEC power-up sequence of LPDDR2, you have to add two 10kOhm pull-down resistors to the CKE0 and CKE1 signals of LPDDR2.

Have a great day,
Artur

[elliottyang]

Thanks a lot

[Yongxin · Accepted solution]

Hi Elliott,

Yes, DRAM_BA0 and DRAM_BA1means DRAM_SDBA0 and DRAM_SDBA1.

The connection is correct.

Since the datasheet didn't mention whether there is internal pull-down of CKE0 and CKE1 in e.MCP, it is recommended to add 10K ohms pull-down resistors in these two pins.

Best Regards,

Yongxin