LPDDR2 2-channel x32 initialization

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LPDDR2 2-channel x32 initialization

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rajeevnair
Contributor II

Hello,

We are using iMX6DL with LPDDR2 (2-channel x32) configuration. We are using micron part MT42L256M64D4LM-25 WT (4 die, each die is 4Gb, each channel is 8Gb). We followed attached reference design shared in SR# 1-1271525975.

We have configured MMDC using the register values from attached xls sheet except we modified the chip select end address (MMDC_MDASP) to indicate each channel size as 1GB.

Observations

1)  We observed that if code (e.g iMX6 Platform SDK) is loaded to 0x80000000 and executed then one can see the serial output but on exection of IPU display test it fails with undefined instruction. However the same code runs without any issue if its loaded to 0x10000000.

2) Similar observation was seen when code was loaded at 0x80000000 and we were performing random value test on 0x10000000 memory region. The code fails with undefined instruction when memory was written btw 0x40000000 to 0x40100000. At this point, it was noted that some sections of code in 0x80000000 region was corrupted. We are not sure whats the reason as the memory test was confined only to 0x10000000 region and within 1GB range.

Questions

1) Should BOOTCFG3[5:4] be configured to 01 to indicate the memory map for LPDDR2 (0x80000000, 0x10000000)? What will be the behavior if MMDC is configured as per the attached xls sheet with BOOTCFG3[5:4] as 00.

2) What is the excepted behavior if we access address beyond the chip select end address? We found that its still possible to read or write to such addresses however not sure if any roll over is happening and to which valid address.

3) If someone has got 2 channel LPDDR2 working, can you pls share the register settings.

Regards

Rajeev

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aven_tsao
NXP Employee
NXP Employee

Hi Rajeev:

For the CS0_END value, the memory size of each channel is 1GB.

But there are 2 chip select in each channel, so the memory size of each chip select should be 512MB and the value of CS0_END should be 512MB

(Please follow the value from xls sheet)

For Q1,

  • Since you are using 2*32Bit LPDDR2, so set BOOTCFG3[5:4] to “01” is suggested, and the MMDC #0 start address will be 0x80000000, MMDC #1 start address will be 0x10000000.
  • When BOOTCFG3[5:4] to “00”, only MMDC #0 is active and the start address will change to 0x10000000. But it will cause the value of CS0_END of MMDC0 incorrect since start address changed.

     Ps. please check the memory address setting in u-boot since the memory start address change.

For Q2

I assume access the address beyond the chip select #0 end means access to chip select #1 area. Since there are 2 chip select in each channel, so access the CS#1 area is workable.

For Q3

Yes, Dual channel  LPDDR2 is verified, please check the memory related setting in your u-boot.

Best regards

Aven

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rajeevnair
Contributor II

Hello Aven,

We tried loading kernel with values channel0 CS0_END=0x4F and channel1 CS0_END= 0x17 as per excel sheet but saw kernel panic during uncompress of initram.

Similar issue with values channel0 CS0_END=0x0F and channel1 CS0_END= 0x0F.

With values channel0 CS0_END=0x1F and channel1 CS0_END= 0x1F, the kernel is getting booted but android crashes during garbage collection.

We are confused now. Can you pls cross-check the settings again as we are suspecting that memory initialization is still not correct?.

Regards

Rajeev

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aven_tsao
NXP Employee
NXP Employee

HI Rajeev:

I think the ddr init script is correct now, and you can use the ddr stress test tool to verify it.

And I assume the problem is the memory mapping settings in u-boot

Sorry that I'm not familiar with the SW side, I can't help for the u-boot modify.

Best regards

Aven.

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rajeevnair
Contributor II

Hello chipexpert,

We see following settings, as suggested by Aven, works. Still we are in process of thorough memory testing.

BOOTCFG3[5:4] = 01

Ch0, CS0_END = 0x4F

Ch1, CS0_END = 0x17

Thanks

Regards

Rajeev

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aven_tsao
NXP Employee
NXP Employee

They are using micron part MT42L256M64D4LM-25 WT (4 die, each die is 4Gb, each channel is 8Gb).

That is Dual channel and Dual Rank device, the memory size of each channel is 1GB, but there are 2 CS in each channel.

So each memory size of each CS is 512MB not 1GB.

Best regards

Aven.

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rajeevnair
Contributor II

Hello Aven,

Thanks for the response.

Still CS0_END aspect is not clear.

The value from sheet

setmem /32 0x021b0040 = 0x0000004F // Chan0 CS0_END

indicates channel0 CS0 will end at 0x4F = 20480Mb = 2.5 GB. With two chip selects for channel 0, the channel0 address range size will be 5 GB but physically there is only 1GB.

setmem /32 0x021b4040 = 0x00000017 // Chan1 CS0_END

indicates channel1 CS0 will end at 0x17 = 6144 Mb = 768 MB. With two chip selects for channel 1, the channel 1 address range size will be 1.5 GB but physically there is only 1GB.

Should CS0_END be 0x0F = 4096Mb = 512 MB?

Similarily CS0_END should be 0x0F.

Regards

Rajeev

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aven_tsao
NXP Employee
NXP Employee

Hi Rajeev:

Please reference to Section 2.3 DDR mapping to MMDC controller in MX6DL RM.

The memory start address is depends on the DDR Memory Map Config [1:0], when the DDR Memory Map Config [1:0] = 0x01.

The MMDC #0 start address is 0x80000000, and the MMDC #1 start address is 0x10000000.

For the CS0_END of MMDC #0,

setmem /32      0x021b0040 =    0x0000004F      // Chan0 CS0_END

It means the CS0 end address is 0x4F=20489Mb= 2560MB=0xA0000000,

The MMDC #0 CS0 address range is 0x80000000 ~0x9FFFFFFF

The MMDC #0 CS1 address range is 0xA0000000 ~0xBFFFFFFF

For the CS1_END of MMDC #0,

setmem /32      0x021b4040 =    0x00000017      // Chan1 CS0_END

It means the CS0 end address is 0x17=6144Mb= 768MB=0x30000000,

The MMDC #1 CS0 address range is 0x10000000 ~0x2FFFFFFF

The MMDC #1 CS1 address range is 0x30000000 ~0x4FFFFFFF

Best regards

Aven

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rajeevnair
Contributor II

Thanks Aven for the illustration.

Its clear now. We should treat CS0_END in terms of absolute address and not relative to MMDC base address.

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