LPDDR Memory Testing Issue on Custom IMX93 Board

[Embedded-world]

Dear Experts,

I'm working on a custom board based on the IMX93. While testing at the U-Boot level, we are using a 2GB LPDDR memory module.

According to the IMX93 Reference Manual, we tested the system memory map using the mtest command from the start address 0x80000000 (NS) to the end address 0xBFFFFFFF (NS). This range is functioning correctly, with both read and write operations working as expected.

But, when performing mtest from 0xC0000000 to 0xFFFFFFFF, it fails, as shown in the diagram below.

i followed the mtest as per the : mtest 

Could you please provide insights into why this issue occurs and possible solutions?

Thanks & Regards 

Ravikumar 

[Embedded-world]

Hi JorgeCas

Yes, I've tested with DDR Data Rate with 1866 Mbps including/excluding multiple set point. so at this case all test are passing without any target board connection issues. 


Thanks & Regards 
Ravikumar

[JorgeCas]

Hello,

You should take DDR tool stress test as final result since there are some RAM sections reserved for the system. Causing writing/reading errors, unexpected reset or system hang.

Best regards.

[Embedded-world]

Hi JorgeCas,

Yes, I tested with the DDR Tool stress test, and it passed. After that, I ran the memory test (mtest) at the boot stage in the console.

Can you tell me which RAM sections are causing the read/write errors?

Thanks & Regards,
Ravikumar

[JorgeCas]

Hello,

Please check it with bdinfo command:

u-boot=> bdinfo
boot_params = 0x0000000000000000
DRAM bank   = 0x0000000000000000
-> start    = 0x0000000080000000
-> size     = 0x0000000016000000
DRAM bank   = 0x0000000000000001
-> start    = 0x0000000098000000
-> size     = 0x0000000068000000
flashstart  = 0x0000000000000000
flashsize   = 0x0000000000000000
flashoffset = 0x0000000000000000
baudrate    = 115200 bps
relocaddr   = 0x00000000feeeb000
reloc off   = 0x000000007eceb000
Build       = 64-bit
current eth = ethernet@428a0000
eth1addr    = 00:04:9f:08:78:d7
IP addr     = <NULL>
fdt_blob    = 0x00000000fcedd730
new_fdt     = 0x00000000fcedd730
fdt_size    = 0x000000000000d640
Video       = lcd-controller@4ae30000 inactive
lmb_dump_all:
 memory.cnt = 0x2 / max = 0x10
 memory[0]      [0x80000000-0x95ffffff], 0x16000000 bytes flags: 0
 memory[1]      [0x98000000-0xffffffff], 0x68000000 bytes flags: 0
 reserved.cnt = 0x2 / max = 0x10
 reserved[0]    [0xfbed3000-0xffffffff], 0x0412d000 bytes flags: 0
 reserved[1]    [0xfced90b0-0xffffffff], 0x03126f50 bytes flags: 0
devicetree  = separate
arch_number = 0x0000000000000000
TLB addr    = 0x00000000fffe0000
irq_sp      = 0x00000000fcedd720
sp start    = 0x00000000fcedd720
Early malloc usage: 16e68 / 18000

Best regards.

[JorgeCas]

Hello,

Did you test LPDDR memory with our stress DDR Tool?

Best regards.