Issue about SSI setting (I2S Master mode) in i.MX6Dual

[keitanagashima]

Dear Sir or Madam,

Customer's board happened below issue.

[Status]

Device: i.MX6D

BSP: Yocto L3.10.17

Board: Custom board

SSI: I2S Master mode

Output: 4ch data output with network mode as normal bit clock + frame

ideal Frame Rate=44.1kHz

[Issue]

Phenomenon: Sound noize from both of Left and Right

Contents: 4ch Wav file(Left-ch:beep sound, Other 3-ch: No sound)

Detail:

- Refer to attached waveform. It looks LRCLK raise up early for 1ch interval.

- This phenomenon was confirmed on SABRE-SDP with custom setting, too.

[Register setting]

Refer to i.MX 6Dual/6Quad Applications Processor Reference Manual(p.5122) "Table 61-7. SSI Bit Clock and Frame

Rate as a Function of PSR, PM, and DIV2"

SSI's sys clock=11.2896MHz, DIV=0, PSR=0, PW=1, WL=7, DC=3

- SSI

　scr=0xbb                // TCH_EN = 0

　sier=0x1b80f00

　stcr=0x2ed             // TFEN0 = 1, TFEN1 = 0

　srcr=0x2cd             // RFEN0 = 1, RFEN1 = 0

　stccr=0xe201

　srccr=0xe201

　sfcsr=0x880688

　stmsk=0xfffffff0

　srmsk=0xfffffff0

- port1(Internal Port)

　ptcr=0x800

　pdcr=0xa000

- port6(External Port)

　ptcr=0x84010800

　pdcr=0x0

[Question]

Q1:

Do you find this cause?

Please give me some advice?

Q2:

Refer to below description.

----------------------------------------------------------------------------------------------------

61.2.1 Signals Overview

SRCK

Serial Receive Clock. SRCK can be used as either an input or an output. This clock signal is used by the receiver

in asynchronous mode and is always continuous. During S, the STCK port is used instead for clocking in data. In

SSI synchronous modes, this port can be used as an output for the network clock (oversampling clock) . In I2S

master mode, this signal can be used to output the network clock to an external CODEC.

----------------------------------------------------------------------------------------------------

I consider that AUD6_RxC(equivalent to SRCK) doesn't have to connect.

Is it right in the following connection?

[Customer's connection]

BCLK(AUD6_TxC)

LRCLK(AUD6_TxFS)

DACDAT(AUD6_TxD)

MCLK(AUD_MCLK)

I attached more detail information.

Please check it, too!

(See attached file: (Detail)Waveform of Audio Codec)

Best Regards,

Keita

[saurabh206]

Hi,

Keita

arch/arm/boot/dts/

arch/arm/mach-imx/mach-imx6q.c

clk_set_rate(pll4_audio_div, 44100*16*512);

[saurabh206]

Hi, Keita

I have modified for JB 4.3 Linux kernel 3.0.35.

You need to make similar modification in 3.10.17 kernel.

Saurabh

[keitanagashima]

Hi Saurabh,

Do you find the location of your mentioned code in 3.10.17 kernel?

BR,

Keita

[keitanagashima]

Hi Saurabh,

Do you find the similar location(code) in 3.10.17 kernel?

BR,

Keita

[fabio_estevam]

Here is a quick workaround I did for getting SSI to work in master mode on imx6q-sabresd running kernel 3.18:

[alsa-devel] No sound captured with SGTL5000 on i.MX6 in I²S master mode

[keitanagashima]

Hi Fabio,

Thank you for your information!

But, my customer had already set your mentioned.

>No sound captured with SGTL ~

Now the MX6Q-SDP output the sound. But it is very noisy.

Best Regards,

Keita

[fabio_estevam]

Hi Keita,

Can they try 3.18-rc4 instead?

[keitanagashima]

Hi Fabio,

>Can they try 3.18-rc4 instead?

Sorry. We can't instead the 3.18-rc4.

BR,

Keita

[keitanagashima]

Hi Fabio,

This issue hadn't resolved.

Is it possible to use the SSI with network mode such a customer's use case in the first place?

Best Regards,

Keita

[keitanagashima]

Dear Sir or Madam,

Please give me your answer asap.

Keita

[saurabh206]

Hi,

Keita

Just make sure that SSI clk and MCLK derived from same clock source.

[keitanagashima]

Hi Saurabh,

Thank you for your reply.

Now, my customer is evaluating it on i.MX6Q SABRE-SDP.

>Just make sure that SSI clk and MCLK derived from same clock source.

"MCLK from GPIO_0(CLKO) && BCLK from AUD3_TXC."

BR,

Keita

[saurabh206]

Hi,

But make sure GPIO clock and AUD_TX3 clock derived from PLL4.

clk_set_parent(clk[ssi1_sel], clk[pll4_audio_div]);

[keitanagashima]

Hi Saurabh,

- SSI1_CLK_ROOT, SSI2_CLK_ROOT, SSI3_CLK_ROOT from PLL4.

- MCLK [ACLK_CLK_ROOT(MIPI_PIXEL_CLK)] from OSC(24M)[pll3_sw_clk)].

BR,

Keita

[saurabh206]

Hi

Keita

static struct clk clko_clk = {

    __INIT_CLK_DEBUG(clko_clk)

    //.parent = &pll2_528_bus_main_clk,

    .parent = &pll4_audio_main_clk,

    .enable = _clk_enable1,

static struct clk ssi1_clk = {

    __INIT_CLK_DEBUG(ssi1_clk)

    //.parent = &pll3_pfd_508M,

    .parent = &pll4_audio_main_clk,

    .enable_reg = MXC_CCM_CCGR5,

clk_set_rate(&pll4_audio_main_clk, /*176000000*/ 180633600);

//44100 base rate --> 44100*8*512 =180633600

Please check above code, I have modified it for 3.0.35 kernel, You need to make modification according to it.

Thanks

Saurabh

[keitanagashima]

Hi Saurabh,

Thank you for your good information.

But, my customer is using L3.10.17 (Yocto).

Where is your mentioned code in L3.10.17_1.0.0 (Yocto)?

BR,

Keita