Is there some restriction for i.MX6DQ ESAI bit-clock?

[satoshishimoda]

Hi community,

I have a question about i.MX6DQ ESAI.

At first, please see Chapter 61.8.4.2 in IMX6DQRM Rev.3.

It shows about the restriction to set bit-clock frequency and register setting (DIV2, PSR and PM) for SSI in the NOTE.

I want to know whether ESAI has similar restriction or not.

I found the restriction when using exterrnal ESAI serial clock in the NOTE of Table 25-3.

But I did not find any restriction when using internal clock.

So I understand ESAI has no restriction for bit-clock frequency and register setting when using internal clock (Fsys or EXTAL) to its clock source.

In other words, I can set TPSR=1b, TPM=0x00, and TFP=0x0 in ESAI_TCCR register at the same time.

Is my understanding correct?

Best Regards,

Satoshi Shimoda

[Yuri · Accepted solution]

Hello,

  According to ESAI_TCCR field descriptions :

"Do not use the combination TPSR=1, TPM7-TPM0=0x00, and TFP3-TFP0=0x0 which

causes synchronization problems when using the internal ARM Core clock as source (TCKD=1 or

THCKD=1)".

Have a great day,
Yuri

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[satoshishimoda]

Dear Yuri,

Thank you for your reply.

Then, I have one more question about the description.

> which causes synchronization problems when using the internal ARM Core clock as source (TCKD=1 or THCKD=1)".

I feel there is no synchronization problems if ETI=1 and EXTAL is lower than 1/4 (or 1/6)  of ARM Core clock (133MHz) even if TCKD=1 or THCKD=1.

In this case, can I use the combination TPSR=1, TPM7-TPM0=0x00, and TFP3-TFP0=0x0?

Best Regards,

Satoshi Shimoda

[Yuri]

Hi,

  Although EXTAL is the on-chip clock sources other than ESAI system, and
may be interpreted as other than ARM Core clock  (which is ipg_clk_esai
in block ESAI), but this clock also is internal one, and it may be fully synchronous

with the ARM Core clock. So, the mentioned issue still may take place.

Regards,

Yuri.

[satoshishimoda]

Dear Yuri,

Thank you for your reply.

OK, I understand the restriction should be applied when using internal clock as ESAI clock source.

Then, how about the case when EXTAL is bypassed external clock which is input to CLK1_P?

For example, input audio master clock (such as 22.5792MHz) to CLK1_P, then PLL4 and all divider in CCM bypass it.

In this case, which is correct?

1. The mentioned issue still may take place since the external clock is synchronized to internal clock by "DIVIDE BY 2" prior to ESAI transmit prescaler which is set by TPSR.

2. We can ignore the mentioned issue since the case is same as when TCKD=0.

Best Regards,

Satoshi Shimoda

[Yuri]

Hello !

     Yes, looks like, Your configuration may work under restrictions for the ESAI external clocks,

but, strictly speaking, the ESAI external clock is assumed as one, provided to specific

external ESAI signals / pins. And restrictions for these clocks concern with relationship

between internal PLL clocks (even with external CLK1 input) and external ESAI clock pins.   

Regards,
Yuri.