Input spec for XTALI pin when using external clock source

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Input spec for XTALI pin when using external clock source

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gavinjones
Contributor I

Dear Forum,

I wish to drive the XTALI pin of the iMX6 with an external clock source. The data sheet states that this is an acceptable thing to do and provides the DC input specifications in section 4.6.1 on page 37 (iMX6 Dual/Quad for Consumer data sheet rev 2.3). One problem is that the Vih value is specified only in terms of NVCC_PLL_OUT. Whilst it is suggested that this is nominally 1.1V, I cannot find a complete specification for NVCC_PLL_OUT. For example, what is the tolerance on this value?

A second problem is that the spec provided for Vih is not very generous and it would be very difficult to strictly meet this spec. The max value is given as equal to NVCC_PLL_OUT. In the Absolute Maximum Ratings (section 4.1.1 on page 19) it suggests that input voltages may exceed the corresponding supply voltage by up to 300mV - is that acceptable for the XTALI input?

Using a potential divider and aiming for a nominal swing of 1.1V, I can provide a clock with the following characteristics:

Max DC high: 1150mV

Min DC high: 1050mV

Max positive overshoot: 1200mV for 500ps.

Min DC low: 0mV

Max DC low: 10mV

Max negative overshoot: -90mV for 500ps.

Is this acceptable for the XTALI input? Do I need to reduce the high level voltage a little?

Thanks,

Gavin.

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jamesbone
NXP TechSupport
NXP TechSupport

NVCC_PLL_OUT it is basically generated by an internal LDO of the i.MX6, ( LDO_1P1).LDO_1P1 - The LDO_1P1 linearly regulates down a higher supply voltage

(2.8V-3.3V from VDD_HIGH_IN) to produce a nominal 1.1V output voltage. This regulator supplies digital portions of USB PHYs, PLLs, and the internal 24MHz oscillator.

VDD_HIGH_IN  oscilates between -0.3v - 3.6v  but the Regulator it is 1.1v with a aprox 80% of swing.

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gavinjones
Contributor I

Hi James,

Thanks for the reply but sadly I do not understand it. You say that VDD_HIGH_IN oscillates - this is a power rail and any oscillation would surely be very bad. The oscillator I was referring to in my question is an external crystal oscillator that is feeding the 24MHz clock into the XTALI pin.

To answer the first part of my question, please can you tell me the minimum and maximum values (accounting for variation due to silicon process, temperature, load regulation, etc) for the NVCC_PLL_OUT output?

Best regards,

Gavin.

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jamesbone
NXP TechSupport
NXP TechSupport

Oh sorry if my communication skills confuse you,  VDD_HIGH_IN it is the power supply of the oscillator. not that oscillates

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gavinjones
Contributor I

Ok, thanks for the clarification.

Returning to my question, in order to obtain a complete input specification for the XTALI pin, I need to know the following:

What is the minimum and maximum values (accounting for variation due to silicon process, temperature, load regulation, etc) for the NVCC_PLL_OUT output?

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jamesbone
NXP TechSupport
NXP TechSupport

Unfortunately we do not have such detail information of the XTAL spec.

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gavinjones
Contributor I

Ok, thanks James.

Given that Freescale are unable to provide an input specification for the XTALI pin, perhaps the assertion that an external clock is supported should be removed from the documentation.

Best regards,

Gavin.

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karina_valencia
NXP Apps Support
NXP Apps Support

jamesbone can you continue with the  follow up on this case?

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