Imx8MN Need help enabling CLKOUT1

[aaloco]

Hi,

I cant get CLKOUT1 to work. I checked the https://community.nxp.com/t5/i-MX-Processors/enable-CLKO2-for-24MHz-output-clock-on-iMX8MN/m-p/12831... patch and made the following changes:

diff --git a/arch/arm64/boot/dts/xxx/xxx.dts b/arch/arm64/boot/dts/xxx/xxx.dts
index 8b6b556996v2..297d3c90042a 100644
--- a/arch/arm64/boot/dts/xxx/xxx.dts
+++ b/arch/arm64/boot/dts/xxx/xxx.dts
@@ -32,6 +32,15 @@ tcan4x5x: tcan4x5x@0 {
};

&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_clkout1>;
+
+ pinctrl_clkout1: clkout1grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59
+ >;
+ };
+
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index f6430d720afc..d08c20117b31 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -638,6 +638,10 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
clk_set_rate(hws[IMX8MN_CLK_AUDIO_AHB]->clk, 400000000);
clk_set_rate(hws[IMX8MN_CLK_IPG_AUDIO_ROOT]->clk, 400000000);

+ //set and enable clko1 24mhz
+ clk_set_parent(clks[IMX8MN_CLK_CLKO1], clks[IMX8MN_CLK_24M]);
+ clk_prepare_enable(clks[IMX8MN_CLK_CLKO1]);
+
imx_register_uart_clocks(4);

return 0;

Anyway i still do not get a clockoutput on GPIO 1 14

[JorgeCas]

Hello,

As is mentioned in the post you are using as reference, the patch was tested using BSP version 5.4.24_2.1.0. There are changes in device tree and clock driver, for example, in the last release, the IOMUX configuration is done in imx8mn-evk.dtsi but in patch version is done in imx8mn-evk.dts.

Also, some functions where renamed, please adapt these changes in your BSP version.

Best regards.

[aaloco]

I tried to adept an now i get 1.8V dc on the testpoint connected to the CLKOUT1 pad (H26).
I am using bsp 6.1.22-2.0.0
What am i doing wrong ?

clk-imx8mn.c:

    hws[IMX8MN_CLK_CLKOUT1_SEL] = imx_clk_hw_mux2("clkout1_sel", base + 0x128, 4, 4, imx8mn_clko1_sels, ARRAY_SIZE(clkout_sels));

    hws[IMX8MN_CLK_CLKOUT1_DIV] = imx_clk_hw_divider("clkout1_div", "clkout1_sel", base + 0x128, 0, 4);

    hws[IMX8MN_CLK_CLKOUT1] = imx_clk_hw_gate("clkout1", "clkout1_div", base + 0x128, 8);

    hws[IMX8MN_CLK_CLKOUT2_SEL] = imx_clk_hw_mux2("clkout2_sel", base + 0x128, 20, 4, imx8mn_clko2_sels, ARRAY_SIZE(clkout_sels));

    hws[IMX8MN_CLK_CLKOUT2_DIV] = imx_clk_hw_divider("clkout2_div", "clkout2_sel", base + 0x128, 16, 4);

hws[IMX8MN_CLK_CLKOUT2] = imx_clk_hw_gate("clkout2", "clkout2_div", base + 0x128, 24);

...

//set and enable clko1 24mhz

    clk_set_parent(hws[IMX8MN_CLK_CLKOUT1]->clk, hws[IMX8MN_CLK_24M]->clk);

    clk_prepare_enable(hws[IMX8MN_CLK_CLKOUT1]->clk);

This is from imx8mn-clock.h i did not change anything here but im just wondering where do these numbers come from?

#define IMX8MN_CLK_WDOG             121

#define IMX8MN_CLK_WRCLK            122

#define IMX8MN_CLK_CLKO1            123

#define IMX8MN_CLK_CLKO2            124

...

#define IMX8MN_CLK_CLKOUT1_SEL          215

#define IMX8MN_CLK_CLKOUT1_DIV          216

#define IMX8MN_CLK_CLKOUT1          217

#define IMX8MN_CLK_CLKOUT2_SEL          218

#define IMX8MN_CLK_CLKOUT2_DIV          219

#define IMX8MN_CLK_CLKOUT2          220