Hello,
As for display clock, please look at section 42.3.10.3 (Timing generator) of the
i.MX51 Reference Manual.
The base signals look as a pulse ___|----|____
This pulse is defined by length (PERIOD), first edge location (UP) and second
edge location (DOWN).
Basically di0/1_clk_root is base clock for display interface. The timebase
(fundamental) of Display clock (DISP_CLK) is configured by using
DI#_DISP_CLK_PERIOD, and then the waveform is created by using the settings
stored in DI#_DISP_CLK_OFFSET, DI#_DISP_CLK_UP and DI#_DISP_CLK_DOWN bit fields.
In addition to the Reference Manual clock scheme is described in the next app
note.
AN4140 : i.MX51 WinCE Clock Setting
< http://cache.freescale.com/files/dsp/doc/app_note/AN4140.pdf >
As we can see, it is possible to use different PLLs for different modules and
one can adapt clocking as needed, without affected other modules.
Have a great day,
Yuri
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