IPU IC register setup for FMem -ch14-> IC -ch21-> DMFC -?-> DP -> DC -> DI to replace FMem -ch23-> DP -> ...?

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IPU IC register setup for FMem -ch14-> IC -ch21-> DMFC -?-> DP -> DC -> DI to replace FMem -ch23-> DP -> ...?

Contributor I

Hi Community,

I have a working setup where I use the channel 23 to display a framebuffer (800x600) from the system memory on the display (LVDS) in 800x600. (FMem -ch23-> DP)

I now want to implement hw scaling using the IC to scale a part of the framebuffer (say 640x480 offset 0x0 within the 800x600 framebuffer) to the complete display of 800x600 resolution. (FMem -ch14-> IC -ch21-> DMFC -?-> DP -> ...)

What registers do I have to set/initialize to switch from a channel 23 setup to one where I inject the IC on runtime?

Here is what I got so far:


2. Set IPU_DMFC_IC_CTRL to replace ch23 (0x4), w: 800, h: 600, ppw: 16 (0x1)

3. Set IC_EN in IPUx_CONF

4. Set Burstsize to 16 for cb3 (ch14) CB3_BURST_16 in IPUx_IC_IDMAC_1

5. Set Burstsize to 16 for cb1 (ch21) CB1_BURST_16 in IPUx_IC_IDMAC_1

6. Set IC output height to 600 T2_FR_HEIGHT in IPUx_IC_IDMAC_2

7. Set IC output width to 800 T2_FR_WIDTH in IPUx_IC_IDMAC_3

8. Set CPMEM of ch14: PFS=0x7 (RGB), BBP=0x3 (16), NPB=0x1f (32 ppb), FW=799, FH=599, WID0=0x4 (5), WID1=0x5 (6), WID2=0x4 (5), WID3=0x7 (8), OFS0=0x0, OFS1=0x5, OFS2=0xB, OFS3=0x10, EBA0=0x1f200000, EBA1=0x1f200000 (Buffer address of ch. 23), Stride=1599

9. Set the IC Task: PRPVF_DS_R_V=0, PRPVF_RS_R_V=0x1996, PRPVF_DS_R_H=0, PRPVF_RS_R_H=0x1997 in IPUx_IC_PRP_VF_RSC=0x19961997 to scale 640x480 to 800x600

10. Setup frame sync flow: PRPVF_DEST_SEL=0x9 (ch23) in IPUx_FS_PROC_FLOW2 and DP_SYNC0_SRC_SEL=0x4 (IC VF) in IPUx_FS_DISP_FLOW1

Not sure if this is right. Do I use ch23 as replacement for ch21 in the sync flow settings?

11. Set the DMFC burstsize for the channel 23 to 4 words: DMFC_FIFO_SIZE_5B=0x11 in IPUx_DMFC_DP_CHAN

12. Enable ch14: IDMAC_CH_EN_14=1 in IPUx_IDMAC_CH_EN_1

13. Enable Viewfinder Task: PRPVF_EN=1 in IPUx_IC_CONF

Did I miss anything or have listed something incorrectly? Do I need to deactivate/change something from the ch23 setup?

The documentation is a bit vague in regards to the channel 21 setup. Does it even use the DP like channel 23 when it replaces channel 23 on the DMFC?

Is a demo/test application with source for this pipeline (FMem->IC->DMFC->...) available?

Thanks and best regards,


added more missing cpmem parameters

added missing DMFC burstsize to 4 words step

3 Replies

NXP TechSupport
NXP TechSupport

Hello cmhe!

Are you still having troubles with this flow?

You may take the i.MX6 Platform SDK as example (Download at www.freescale.com).

Please, check the document inside the i.MX6 Platform SDK package called "iMX6_Firmware_Guide.pdf" chapter 18.10.4. It describes the use case and provides the source code. Seems to be exactly the usecase you want to implement, using IC to resize and DMFC.

If you don't find the package, let us know.

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Contributor I

Hi husarambula,

thanks for your aswer, but I didn't solved my problem using this approach, instead I now use FMem->IC->FMem->DP->DC->DI which works in my case and give me more flexibility.

I don't have time to test this solution again, but here are some pointers for people having the same issue:

One thing I might have missing in the above flow is setting the VF_IN_VALID bit in IPUx_FS_PROC_FLOW1 and IC_INPUT bit in IPUx_CONF.

Also instead of the preprocessing flow the viewfinder flow should be used, e.g. channel 12 instead of 14, and change in the task accordingly.

The stride value was wrong too.



NXP TechSupport
NXP TechSupport

Hello cmhe,

Thank you for posting your findings! I'm sure these will help other users!

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