IMX8X PPS output configuration

[rbeims]

We have been trying to make the PPS output work on a Colibri iMX8X. We have added the mux settings for the PPS output pin:

+/* Colibri Ethernet: On-module 100Mbps PHY Micrel KSZ8041 */
+&pinctrl_fec1 {
+	fsl,pins = <
+		IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD	0x000014a0 /* Use pads in 3.3V mode */
+		IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD	0x000014a0 /* Use pads in 3.3V mode */
+		IMX8QXP_ENET0_MDC_CONN_ENET0_MDC		0x06000020
+		IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO		0x06000020
+		IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x61
+		IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT	0x06000061
+		IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x61
+		IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x61
+		IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x61
+		IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x61
+		IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x61
+		IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER	0x61
+		IMX8QXP_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS	0x21
+	>;
+};

But this was not sufficient to get the PPS working. After more investigation, we found out that if we change the #define DEFAULT_PPS_CHANNEL on drivers/net/ethernet/freescale/fec_ptp.c from 0 to 1 the output starts to work.

I researched the documentation trying to find how to define the association of an IEEE1588_TMR instance with the respective PPS output but I couldn't see any description of this.

I saw that there are 4 IEEE1588 channels that are available on the iMX8X, but we only have two PPS outputs, and from their descriptions, it seems that each one is associated with only one of the FEC's:

IMX8QXP_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS and IMX8QXP_ENET0_REFCLK_125M_25M_CONN_ENET1_PPS

With this I ask:

What is the association between the IEEE1588 timer channel and the PPS output?

Can this be changed somehow (i.e. map the IEEE1588 channel 0 to the IMX8QXP_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS)?

We know now that for some reason channel 1 is mapped IMX8QXP_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS. With this reasoning, can we say that channel 3 is mapped to IMX8QXP_ENET0_REFCLK_125M_25M_CONN_ENET1_PPS, and the even channels are restricted to software-only capture modes?

Any help will be appreciated,

Rafael